Palkesh JAIN

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Configurable redundant systems for safety critical applications
- Patent number 11,424,621
- Issue date Aug 23, 2022
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-field monitoring of on-chip thermal, power distribution network,...
- Patent number 11,416,049
- Issue date Aug 16, 2022
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital duty-cycle monitoring of a periodic signal
- Patent number 10,901,020
- Issue date Jan 26, 2021
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for context-aware thermal management and workload...
- Patent number 10,591,965
- Issue date Mar 17, 2020
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correcting code testing
- Patent number 10,389,379
- Issue date Aug 20, 2019
- QUALCOMM Incorporated
- Rahul Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated device comprising device level cells with variable sizes...
- Patent number 10,141,297
- Issue date Nov 27, 2018
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjust voltage for thermal mitigation
- Patent number 10,103,714
- Issue date Oct 16, 2018
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for false pass detection in lockstep dual core or...
- Patent number 10,089,194
- Issue date Oct 2, 2018
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjusting source voltage based on stored information
- Patent number 10,042,405
- Issue date Aug 7, 2018
- QUALCOMM Incorporated
- Palkesh Jain
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Systems and methods for adaptive clock design
- Patent number 9,915,968
- Issue date Mar 13, 2018
- QUALCOMM Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ultra-fast autonomous clock monitoring circuit for safe and secure...
- Patent number 9,897,651
- Issue date Feb 20, 2018
- QUALCOMM Incorporated
- Virendra Bansal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cell-level signal electromigration
- Patent number 9,665,680
- Issue date May 30, 2017
- Regents of The University of Minnesota
- Sachin S. Sapatnekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supply voltage tracking clock generator in adaptive clock distribut...
- Patent number 9,628,089
- Issue date Apr 18, 2017
- QUALCOMM Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bias temperature instability-resistant circuits
- Patent number 8,786,307
- Issue date Jul 22, 2014
- Texas Instruments Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electromigration compensation system
- Patent number 8,677,303
- Issue date Mar 18, 2014
- Texas Instruments Incorporated
- Palkesh Jain
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for designing a semiconductor device based on leakage curren...
- Patent number 8,296,701
- Issue date Oct 23, 2012
- Texas Instruments Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabricating IC with NBTI path delay within timing constraints
- Patent number 8,255,850
- Issue date Aug 28, 2012
- Texas Instruments Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Budgeting electromigration-related reliability among metal paths in...
- Patent number 8,219,953
- Issue date Jul 10, 2012
- Texas Instruments Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-mode circuit and a method for preventing degradation in the m...
- Patent number 8,013,635
- Issue date Sep 6, 2011
- Texas Instruments Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SEU hardening circuit and method
- Patent number 7,791,926
- Issue date Sep 7, 2010
- Texas Instruments Incorporated
- Palkesh Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for determining electro-migration in integrate...
- Patent number 7,752,582
- Issue date Jul 6, 2010
- Texas Instruments Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for aging induced performance drift compensation in an in...
- Patent number 7,689,377
- Issue date Mar 30, 2010
- Texas Instruments Incorporated
- Palkesh Jain
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
In-field Monitoring of On-Chip Thermal, Power Distribution Network,...
- Publication number 20210294398
- Publication date Sep 23, 2021
- QUALCOMM Incorporated
- Palkesh JAIN
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURABLE REDUNDANT SYSTEMS FOR SAFETY CRITICAL APPLICATIONS
- Publication number 20210234376
- Publication date Jul 29, 2021
- QUALCOMM Incorporated
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL DUTY-CYCLE MONITORING OF A PERIODIC SIGNAL
- Publication number 20200072885
- Publication date Mar 5, 2020
- QUALCOMM Incorporated
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIVERSE REDUNDANT PROCESSING MODULES FOR ERROR DETECTION
- Publication number 20200019477
- Publication date Jan 16, 2020
- QUALCOMM Incorporated
- Palkesh JAIN
- G01 - MEASURING TESTING
Information Patent Application
ERROR CORRECTING CODE TESTING
- Publication number 20180331692
- Publication date Nov 15, 2018
- QUALCOMM Incorporated
- Rahul GULATI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR CONTEXT-AWARE THERMAL MANAGEMENT AND WORKLOAD...
- Publication number 20180210522
- Publication date Jul 26, 2018
- QUALCOMM Incorporated
- PALKESH JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuits and Methods Providing Thread Assignment for a Multi-Core P...
- Publication number 20180143862
- Publication date May 24, 2018
- QUALCOMM Incorporated
- Mehdi Saeidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR FALSE PASS DETECTION IN LOCKSTEP DUAL CORE OR...
- Publication number 20170357557
- Publication date Dec 14, 2017
- QUALCOMM Incorporated
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROBABILISTIC THERMAL HOTSPOT ACCOMMODATION
- Publication number 20170308637
- Publication date Oct 26, 2017
- QUALCOMM Incorporated
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ADAPTIVE CLOCK DESIGN
- Publication number 20170300080
- Publication date Oct 19, 2017
- QUALCOMM Incorporated
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUST VOLTAGE FOR THERMAL MITIGATION
- Publication number 20170257079
- Publication date Sep 7, 2017
- QUALCOMM Incorporated
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ultra-Fast Autonomous Clock Monitoring Circuit for Safe and Secure...
- Publication number 20170255223
- Publication date Sep 7, 2017
- QUALCOMM Incorporated
- Virendra Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHORT-RESISTANT OUTPUT PIN CIRCUITRY
- Publication number 20170222430
- Publication date Aug 3, 2017
- QUALCOMM Incorporated
- Virendra Bansal
- G01 - MEASURING TESTING
Information Patent Application
ADJUSTING SOURCE VOLTAGE BASED ON STORED INFORMATION
- Publication number 20170115710
- Publication date Apr 27, 2017
- QUALCOMM Incorporated
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STOCHASTIC AND TOPOLOGICALLY AWARE ELECTROMIGRATION ANALYSIS METHOD...
- Publication number 20160116527
- Publication date Apr 28, 2016
- QUALCOMM Incorporated
- Palkesh Jain
- G01 - MEASURING TESTING
Information Patent Application
Cell-Level Signal Electromigration
- Publication number 20150347665
- Publication date Dec 3, 2015
- Regents of the University of Minnesota
- Sachin S. Sapatnekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DIE AND METHOD OF MAKING
- Publication number 20140024144
- Publication date Jan 23, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DIE AND METHOD OF MAKING
- Publication number 20130161718
- Publication date Jun 27, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS
- Publication number 20130002327
- Publication date Jan 3, 2013
- Texas Instruments, Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS
- Publication number 20130002297
- Publication date Jan 3, 2013
- Texas Instruments, Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIA...
- Publication number 20120266123
- Publication date Oct 18, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE BASED ON LEAKAGE CURREN...
- Publication number 20120167031
- Publication date Jun 28, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE M...
- Publication number 20110193588
- Publication date Aug 11, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTROMIGRATION COMPENSATION SYSTEM
- Publication number 20110080175
- Publication date Apr 7, 2011
- PALKESH JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN OF INTEGRATED CIRCUITS LESS SUSCEPTIBLE TO DEGRADATIONS IN T...
- Publication number 20090187868
- Publication date Jul 23, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Budgeting Electromigration-Related Reliability Among Metal Paths In...
- Publication number 20090187869
- Publication date Jul 23, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Burn-In Tests To Produce Fabricated Integrated Circuits With Reduce...
- Publication number 20090187368
- Publication date Jul 23, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh Jain
- G01 - MEASURING TESTING
Information Patent Application
SEU HARDENING CIRCUIT AND METHOD
- Publication number 20090135643
- Publication date May 28, 2009
- PALKESH JAIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR DETERMINING ELECTRO-MIGRATION IN INTEGRAT...
- Publication number 20090132972
- Publication date May 21, 2009
- PALKESH JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR AGING INDUCED PERFORMANCE DRIFT COMPENSATION IN AN IN...
- Publication number 20080116455
- Publication date May 22, 2008
- PALKESH JAIN
- H03 - BASIC ELECTRONIC CIRCUITRY

Palkesh JAIN

Person

Patents Grantslast 30 patents

Configurable redundant systems for safety critical applications

In-field monitoring of on-chip thermal, power distribution network,...

Digital duty-cycle monitoring of a periodic signal

System and method for context-aware thermal management and workload...

Error correcting code testing

Integrated device comprising device level cells with variable sizes...

Adjust voltage for thermal mitigation

System and method for false pass detection in lockstep dual core or...

Adjusting source voltage based on stored information

Systems and methods for adaptive clock design

Ultra-fast autonomous clock monitoring circuit for safe and secure...

Cell-level signal electromigration

Supply voltage tracking clock generator in adaptive clock distribut...

Bias temperature instability-resistant circuits

Electromigration compensation system

Method for designing a semiconductor device based on leakage curren...

Fabricating IC with NBTI path delay within timing constraints

Budgeting electromigration-related reliability among metal paths in...

Multi-mode circuit and a method for preventing degradation in the m...

SEU hardening circuit and method

Method and apparatus for determining electro-migration in integrate...

Technique for aging induced performance drift compensation in an in...

Patents Applicationslast 30 patents

In-field Monitoring of On-Chip Thermal, Power Distribution Network,...

CONFIGURABLE REDUNDANT SYSTEMS FOR SAFETY CRITICAL APPLICATIONS

DIGITAL DUTY-CYCLE MONITORING OF A PERIODIC SIGNAL

DIVERSE REDUNDANT PROCESSING MODULES FOR ERROR DETECTION

ERROR CORRECTING CODE TESTING

SYSTEM AND METHOD FOR CONTEXT-AWARE THERMAL MANAGEMENT AND WORKLOAD...

Circuits and Methods Providing Thread Assignment for a Multi-Core P...

SYSTEM AND METHOD FOR FALSE PASS DETECTION IN LOCKSTEP DUAL CORE OR...

PROBABILISTIC THERMAL HOTSPOT ACCOMMODATION

SYSTEMS AND METHODS FOR ADAPTIVE CLOCK DESIGN

ADJUST VOLTAGE FOR THERMAL MITIGATION

Ultra-Fast Autonomous Clock Monitoring Circuit for Safe and Secure...

SHORT-RESISTANT OUTPUT PIN CIRCUITRY

ADJUSTING SOURCE VOLTAGE BASED ON STORED INFORMATION

STOCHASTIC AND TOPOLOGICALLY AWARE ELECTROMIGRATION ANALYSIS METHOD...

Cell-Level Signal Electromigration

INTEGRATED CIRCUIT DIE AND METHOD OF MAKING

INTEGRATED CIRCUIT DIE AND METHOD OF MAKING

BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS

BIAS TEMPERATURE INSTABILITY-RESISTANT CIRCUITS

COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIA...

METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE BASED ON LEAKAGE CURREN...

MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE M...

ELECTROMIGRATION COMPENSATION SYSTEM

DESIGN OF INTEGRATED CIRCUITS LESS SUSCEPTIBLE TO DEGRADATIONS IN T...

Budgeting Electromigration-Related Reliability Among Metal Paths In...

Burn-In Tests To Produce Fabricated Integrated Circuits With Reduce...

SEU HARDENING CIRCUIT AND METHOD

METHOD AND APPARATUS FOR DETERMINING ELECTRO-MIGRATION IN INTEGRAT...

TECHNIQUE FOR AGING INDUCED PERFORMANCE DRIFT COMPENSATION IN AN IN...