Pankaj DESHMUKH

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple-core memory controller
- Patent number 12,153,531
- Issue date Nov 26, 2024
- QUALCOMM Incorporated
- Pankaj Deshmukh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic random access memory (DRAM) row hammering mitigation
- Patent number 12,094,515
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Victor Van Der Veen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system with adaptive refresh
- Patent number 12,038,855
- Issue date Jul 16, 2024
- QUALCOMM Incorporated
- Pankaj Deshmukh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible dual ranks memory system to boost performance
- Patent number 11,907,141
- Issue date Feb 20, 2024
- QUALCOMM Incorporated
- Jungwon Suh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency in pseudo channel based memory systems
- Patent number 11,893,240
- Issue date Feb 6, 2024
- QUALCOMM Incorporated
- Shyamkumar Thoziyoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive memory access management
- Patent number 11,360,897
- Issue date Jun 14, 2022
- QUALCOMM Incorporated
- Jungwon Suh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SYSTEM WITH ADAPTIVE REFRESH
- Publication number 20240311317
- Publication date Sep 19, 2024
- QUALCOMM Incorporated
- Pankaj Deshmukh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-CORE MEMORY CONTROLLER
- Publication number 20240176751
- Publication date May 30, 2024
- QUALCOMM Incorporated
- Pankaj Deshmukh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METADATA REGISTERS FOR A MEMORY DEVICE
- Publication number 20240126438
- Publication date Apr 18, 2024
- QUALCOMM Incorporated
- Jungwon Suh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS
- Publication number 20240111424
- Publication date Apr 4, 2024
- QUALCOMM Incorporated
- Shyamkumar THOZIYOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC ROWHAMMER MANAGEMENT
- Publication number 20240087639
- Publication date Mar 14, 2024
- QUALCOMM Incorporated
- Victor VAN DER VEEN
- G11 - INFORMATION STORAGE
Information Patent Application
Flexible Dual Ranks Memory System To Boost Performance
- Publication number 20240078202
- Publication date Mar 7, 2024
- QUALCOMM Incorporated
- Jungwon SUH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW HAMMERING MITIGATION
- Publication number 20240062800
- Publication date Feb 22, 2024
- QUALCOMM Incorporated
- Victor Van Der Veen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM WITH ADAPTIVE REFRESH
- Publication number 20230305971
- Publication date Sep 28, 2023
- QUALCOMM Incorporated
- Pankaj Deshmukh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reducing Latency In Pseudo Channel Based Memory Systems
- Publication number 20230136996
- Publication date May 4, 2023
- QUALCOMM Incorporated
- Shyamkumar THOZIYOOR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM WITH QUICK RANDOM ROW REFRESH FOR ROWHAMMER MITIGATION
- Publication number 20220129200
- Publication date Apr 28, 2022
- Qualcomm Incorporated
- Victor VAN DER VEEN
- G06 - COMPUTING CALCULATING COUNTING

Pankaj DESHMUKH

Person

Patents Grantslast 30 patents

Multiple-core memory controller

Dynamic random access memory (DRAM) row hammering mitigation

Memory system with adaptive refresh

Flexible dual ranks memory system to boost performance

Reducing latency in pseudo channel based memory systems

Adaptive memory access management

Patents Applicationslast 30 patents

MEMORY SYSTEM WITH ADAPTIVE REFRESH

MULTIPLE-CORE MEMORY CONTROLLER

METADATA REGISTERS FOR A MEMORY DEVICE

REDUCING LATENCY IN PSEUDO CHANNEL BASED MEMORY SYSTEMS

DYNAMIC ROWHAMMER MANAGEMENT

Flexible Dual Ranks Memory System To Boost Performance

DYNAMIC RANDOM ACCESS MEMORY (DRAM) ROW HAMMERING MITIGATION

MEMORY SYSTEM WITH ADAPTIVE REFRESH

Reducing Latency In Pseudo Channel Based Memory Systems

DRAM WITH QUICK RANDOM ROW REFRESH FOR ROWHAMMER MITIGATION