Pao-Lu Louis Huang

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Logic soft error rate prediction and improvement
- Patent number 7,644,311
- Issue date Jan 5, 2010
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G01 - MEASURING TESTING
Information Patent Grant
Method for improved single event latch up resistance in an integrat...
- Patent number 7,474,011
- Issue date Jan 6, 2009
- Integrated Device Technologies, inc.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual port memory cell with reduced coupling capacitance and small c...
- Patent number 7,286,438
- Issue date Oct 23, 2007
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method for improved single event latch up resistance in an integrat...
- Publication number 20080122473
- Publication date May 29, 2008
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic soft error rate prediction and improvement
- Publication number 20070234125
- Publication date Oct 4, 2007
- Chuen-Der Lien
- G01 - MEASURING TESTING
Information Patent Application
Dual port memory cell with reduced coupling capacitance and small c...
- Publication number 20060227649
- Publication date Oct 12, 2006
- Integrated Device Technology, Inc.
- Chuen-Der Lien
- G11 - INFORMATION STORAGE