Parivallal Kannan

Person

Longmont, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Signal routing and pin placement
- Patent number 8,196,082
- Issue date Jun 5, 2012
- Xilinx, Inc.
- Parivallal Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Congestion elimination using adaptive cost schedule to route signal...
- Patent number 8,122,420
- Issue date Feb 21, 2012
- Xilinx, Inc.
- Parivallal Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assignment of select input/output blocks to banks for integrated ci...
- Patent number 8,010,924
- Issue date Aug 30, 2011
- Xilinx, Inc.
- Victor Z. Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of I/O blocks within I/O banks using an integer linear pr...
- Patent number 7,958,480
- Issue date Jun 7, 2011
- Xilinx, Inc.
- Victor Z. Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recursive partitioning based placement for programmable logic devic...
- Patent number 7,530,045
- Issue date May 5, 2009
- Xilinx, Inc.
- Parivallal Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Skew-driven routing for networks
- Patent number 7,516,437
- Issue date Apr 7, 2009
- Xilinx, Inc.
- Parivallal Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assignment of select I/O objects to banks with mixed capacities usi...
- Patent number 7,480,884
- Issue date Jan 20, 2009
- Xilinx, Inc.
- Victor Z. Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous assignment of select I/O objects and clock I/O objects...
- Patent number 7,451,422
- Issue date Nov 11, 2008
- Xilinx, Inc.
- Victor Z. Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of flexible clock placement for integrated circuit designs u...
- Patent number 7,353,485
- Issue date Apr 1, 2008
- Xilinx, Inc.
- Parivallal Kannan
- G06 - COMPUTING CALCULATING COUNTING

Parivallal Kannan

Person

Patents Grantslast 30 patents

Signal routing and pin placement

Congestion elimination using adaptive cost schedule to route signal...

Assignment of select input/output blocks to banks for integrated ci...

Placement of I/O blocks within I/O banks using an integer linear pr...

Recursive partitioning based placement for programmable logic devic...

Skew-driven routing for networks

Assignment of select I/O objects to banks with mixed capacities usi...

Simultaneous assignment of select I/O objects and clock I/O objects...

Method of flexible clock placement for integrated circuit designs u...