Parivallal Kannan

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Balanced partitioning of neural network based on execution latencies
- Patent number 11,797,280
- Issue date Oct 24, 2023
- Amazon Technologies, Inc.
- Parivallal Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing optimizations in circuit designs using opposite clock edge t...
- Patent number 10,416,232
- Issue date Sep 17, 2019
- Xilinx, Inc.
- Guenter Stenz
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fixing hold time violations using hold time budgets and slacks of s...
- Patent number 10,318,699
- Issue date Jun 11, 2019
- Xilinx, Inc.
- Satish B. Sivaswamy
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MICRO-NETWORK-ON-CHIP AND MICROSECTOR INFRASTRUCTURE
- Publication number 20220197855
- Publication date Jun 23, 2022
- Intel Corporation
- Ilya K. Ganusov
- G06 - COMPUTING CALCULATING COUNTING