Parthajit Bhattacharya

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Mapping physical shift failures to scan cells for detecting physica...
- Patent number 10,605,863
- Issue date Mar 31, 2020
- Synopsys, Inc.
- Subhadip Kundu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling of undesirable distribution of unknown values in testing o...
- Patent number 10,067,187
- Issue date Sep 4, 2018
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Identifying failure indicating scan test cells of a circuit-under-test
- Patent number 9,568,550
- Issue date Feb 14, 2017
- Synopsys, Inc.
- Subhadip Kundu
- G01 - MEASURING TESTING
Information Patent Grant
Scheme for masking output of scan chains in test circuit
- Patent number 9,417,287
- Issue date Aug 16, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Reordering or removal of test patterns for detecting faults in inte...
- Patent number 9,411,014
- Issue date Aug 9, 2016
- Synopsys, Inc.
- Sushovan Podder
- G01 - MEASURING TESTING
Information Patent Grant
Localizing fault flop in circuit by using modified test pattern
- Patent number 9,329,235
- Issue date May 3, 2016
- Synopsys, Inc.
- Parthajit Bhattacharya
- G01 - MEASURING TESTING
Information Patent Grant
Accelerating automatic test pattern generation in a multi-core comp...
- Patent number 8,521,464
- Issue date Aug 27, 2013
- Synopsys, Inc.
- Ashwin Kumar
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
MAPPING PHYSICAL SHIFT FAILURES TO SCAN CELLS FOR DETECTING PHYSICA...
- Publication number 20180267098
- Publication date Sep 20, 2018
- Synopsys, Inc.
- Subhadip Kundu
- G01 - MEASURING TESTING
Information Patent Application
IDENTIFYING FAILURE INDICATING SCAN TEST CELLS OF A CIRCUIT-UNDER-TEST
- Publication number 20170059651
- Publication date Mar 2, 2017
- Synopsys, Inc.
- Subhadip Kundu
- G01 - MEASURING TESTING
Information Patent Application
Scheme for Masking Output of Scan Chains in Test Circuit
- Publication number 20160341795
- Publication date Nov 24, 2016
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Handling of Undesirable Distribution of Unknown Values in Testing o...
- Publication number 20150025819
- Publication date Jan 22, 2015
- Synopsys, Inc.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Reordering or Removal of Test Patterns for Detecting Faults in Inte...
- Publication number 20140289579
- Publication date Sep 25, 2014
- Sushovan Podder
- G01 - MEASURING TESTING
Information Patent Application
Localizing Fault Flop in Circuit by Using Modified Test Pattern
- Publication number 20140281777
- Publication date Sep 18, 2014
- Synopsys, Inc.
- Parthajit Bhattacharya
- G01 - MEASURING TESTING
Information Patent Application
Accelerating Automatic Test Pattern Generation in a Multi-Core Comp...
- Publication number 20110301907
- Publication date Dec 8, 2011
- Synopsys, Inc.
- Ashwin Kumar
- G01 - MEASURING TESTING

Parthajit Bhattacharya

Person

Patents Grantslast 30 patents

Mapping physical shift failures to scan cells for detecting physica...

Handling of undesirable distribution of unknown values in testing o...

Identifying failure indicating scan test cells of a circuit-under-test

Scheme for masking output of scan chains in test circuit

Reordering or removal of test patterns for detecting faults in inte...

Localizing fault flop in circuit by using modified test pattern

Accelerating automatic test pattern generation in a multi-core comp...

Patents Applicationslast 30 patents

MAPPING PHYSICAL SHIFT FAILURES TO SCAN CELLS FOR DETECTING PHYSICA...

IDENTIFYING FAILURE INDICATING SCAN TEST CELLS OF A CIRCUIT-UNDER-TEST

Scheme for Masking Output of Scan Chains in Test Circuit

Handling of Undesirable Distribution of Unknown Values in Testing o...

Reordering or Removal of Test Patterns for Detecting Faults in Inte...

Localizing Fault Flop in Circuit by Using Modified Test Pattern

Accelerating Automatic Test Pattern Generation in a Multi-Core Comp...