Patrick Isakanian

Person

El Dorado Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock qualifier enhancement for external double data rate memory in...
- Patent number 12,100,474
- Issue date Sep 24, 2024
- QUALCOMM Incorporated
- Yong Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Decision feedback equalizer for low-voltage high-speed serial links
- Patent number 11,962,440
- Issue date Apr 16, 2024
- QUALCOMM Incorporated
- Darius Valaee
- G11 - INFORMATION STORAGE
Information Patent Grant
Timer-based edge-boosting equalizer for high-speed wireline transmi...
- Patent number 11,824,695
- Issue date Nov 21, 2023
- QUALCOMM Incorporated
- Darius Valaee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit device aging assessment and compensation
- Patent number 11,637,553
- Issue date Apr 25, 2023
- Qualcomm Incorpoated
- Patrick Isakanian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit device aging assessment and compensation
- Patent number 11,381,238
- Issue date Jul 5, 2022
- QUALCOMM Incorporated
- Patrick Isakanian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Equalization for a transmitter circuit
- Patent number 11,018,904
- Issue date May 25, 2021
- QUALCOMM Incorporated
- Prince Mathew
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface with adjustable voltage and termination and method...
- Patent number 10,613,613
- Issue date Apr 7, 2020
- QUALCOMM Incorporated
- Michael Brunolli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface with adjustable voltage and termination and method...
- Patent number 9,910,482
- Issue date Mar 6, 2018
- QUALCOMM Incorporated
- Michael Brunolli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transistors configured for gate overbiasing and circuits therefrom
- Patent number 9,762,231
- Issue date Sep 12, 2017
- QUALCOMM Incorporated
- Alvin Leng Sun Loke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Constant impedance transmitter with variable output voltage limits
- Patent number 9,762,237
- Issue date Sep 12, 2017
- QUALCOMM Incorporated
- Patrick Isakanian
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT INTEGRATION OF T-COILS AT INTERFACES TO COMMUNIC...
- Publication number 20240235188
- Publication date Jul 11, 2024
- QUALCOMM Incorporated
- Patrick ISAKANIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT INTEGRATION OF T-COILS AT INTERFACES TO COMMUNIC...
- Publication number 20240136812
- Publication date Apr 25, 2024
- QUALCOMM Incorporated
- Patrick ISAKANIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID LOW POWER RAIL TO RAIL AMPLIFIER WITH LEAKAGE CONTROL
- Publication number 20240128941
- Publication date Apr 18, 2024
- QUALCOMM Incorporated
- Armina KHAKPOUR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK QUALIFIER ENHANCEMENT FOR EXTERNAL DOUBLE DATA RATE MEMORY IN...
- Publication number 20240105243
- Publication date Mar 28, 2024
- QUALCOMM Incorporated
- Yong XU
- G11 - INFORMATION STORAGE
Information Patent Application
TIMER-BASED EDGE-BOOSTING EQUALIZER FOR HIGH-SPEED WIRELINE TRANSMI...
- Publication number 20230275792
- Publication date Aug 31, 2023
- QUALCOMM Incorporated
- Darius VALAEE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DECISION FEEDBACK EQUALIZER FOR LOW-VOLTAGE HIGH-SPEED SERIAL LINKS
- Publication number 20230188388
- Publication date Jun 15, 2023
- QUALCOMM Incorporated
- Darius VALAEE
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT DEVICE AGING ASSESSMENT AND COMPENSATION
- Publication number 20220393679
- Publication date Dec 8, 2022
- QUALCOMM Incorporated
- Patrick ISAKANIAN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHOD...
- Publication number 20180129267
- Publication date May 10, 2018
- QUALCOMM Incorporated
- Michael BRUNOLLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHOD...
- Publication number 20170090546
- Publication date Mar 30, 2017
- QUALCOMM Incorporated
- Michael Brunolli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRIVER USING PULL-UP NMOS TRANSISTOR
- Publication number 20160285453
- Publication date Sep 29, 2016
- QUALCOMM Incorporated
- Stephen Clifford Thilenius
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM
- Publication number 20160269017
- Publication date Sep 15, 2016
- Alvin Leng Sun Loke
- H03 - BASIC ELECTRONIC CIRCUITRY

Patrick Isakanian

Person

Patents Grantslast 30 patents

Clock qualifier enhancement for external double data rate memory in...

Decision feedback equalizer for low-voltage high-speed serial links

Timer-based edge-boosting equalizer for high-speed wireline transmi...

Circuit device aging assessment and compensation

Circuit device aging assessment and compensation

Equalization for a transmitter circuit

Memory interface with adjustable voltage and termination and method...

Memory interface with adjustable voltage and termination and method...

Transistors configured for gate overbiasing and circuits therefrom

Constant impedance transmitter with variable output voltage limits

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT INTEGRATION OF T-COILS AT INTERFACES TO COMMUNIC...

INTEGRATED CIRCUIT INTEGRATION OF T-COILS AT INTERFACES TO COMMUNIC...

HYBRID LOW POWER RAIL TO RAIL AMPLIFIER WITH LEAKAGE CONTROL

CLOCK QUALIFIER ENHANCEMENT FOR EXTERNAL DOUBLE DATA RATE MEMORY IN...

TIMER-BASED EDGE-BOOSTING EQUALIZER FOR HIGH-SPEED WIRELINE TRANSMI...

DECISION FEEDBACK EQUALIZER FOR LOW-VOLTAGE HIGH-SPEED SERIAL LINKS

CIRCUIT DEVICE AGING ASSESSMENT AND COMPENSATION

MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHOD...

MEMORY INTERFACE WITH ADJUSTABLE VOLTAGE AND TERMINATION AND METHOD...

DRIVER USING PULL-UP NMOS TRANSISTOR

TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM