Patrick J. Meaney

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cable pair concurrent servicing
- Patent number 11,960,426
- Issue date Apr 16, 2024
- International Business Machines Corporation
- Rajat Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency deserializer having fine granularity and defective-lane...
- Patent number 11,907,074
- Issue date Feb 20, 2024
- International Business Machines Corporation
- Patrick James Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host synchronized autonomous data chip address sequencer for a dist...
- Patent number 11,687,254
- Issue date Jun 27, 2023
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency, high-availability and high-speed SerDes interface havi...
- Patent number 11,646,861
- Issue date May 9, 2023
- International Business Machines Corporation
- Patrick James Meaney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low latency availability in degraded redundant array of independent...
- Patent number 11,609,817
- Issue date Mar 21, 2023
- International Business Machines Corporation
- Patrick James Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip controlled data chip address sequencing for a...
- Patent number 11,587,600
- Issue date Feb 21, 2023
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Refresh-hiding memory system staggered refresh
- Patent number 11,520,659
- Issue date Dec 6, 2022
- International Business Machines Corporation
- Patrick James Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 11,379,123
- Issue date Jul 5, 2022
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency availability in degraded redundant array of independent...
- Patent number 11,200,119
- Issue date Dec 14, 2021
- International Business Machines Corporation
- Patrick James Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a cyclic redundancy code multiple-input shift register to pr...
- Patent number 11,088,782
- Issue date Aug 10, 2021
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 10,976,939
- Issue date Apr 13, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common high and low random bit error correction logic
- Patent number 10,901,839
- Issue date Jan 26, 2021
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common high and low random bit error correction logic
- Patent number 10,824,504
- Issue date Nov 3, 2020
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High efficiency redundant array of independent memory
- Patent number 10,824,508
- Issue date Nov 3, 2020
- International Business Machines Corporation
- Patrick J. Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host controlled data chip address sequencing for a distributed memo...
- Patent number 10,747,442
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional memory spreading for heterogeneous memory sizes
- Patent number 10,684,968
- Issue date Jun 16, 2020
- International Business Machines Corporation
- David D. Cadigan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic time-domain reflectometry analysis for field replaceable un...
- Patent number 10,673,732
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Luiz C. Alves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic time-domain reflectometry analysis for field replaceable un...
- Patent number 10,666,540
- Issue date May 26, 2020
- International Business Machines Corporation
- Luiz C. Alves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register access in a distributed memory buffer system
- Patent number 10,642,535
- Issue date May 5, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory mirror invocation upon detecting a correctable error
- Patent number 10,613,951
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Marc A. Gollub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction potency improvement via added burst beats in a dra...
- Patent number 10,606,692
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced latency error correction decoding
- Patent number 10,601,448
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Glenn Gilda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power-reduced redundant array of independent memory (RAIM) system
- Patent number 10,558,519
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Glenn D. Gilda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a cyclic redundancy code multiple-input shift register to pr...
- Patent number 10,541,782
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Host synchronized autonomous data chip address sequencer for a dist...
- Patent number 10,534,555
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically adjustable cyclic redundancy code types
- Patent number 10,530,396
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically adjustable cyclic redundancy code rates
- Patent number 10,530,523
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 10,489,069
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of multiple cyclic redundancy codes for optimized fail isolation
- Patent number 10,419,035
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Address/command chip controlled data chip address sequencing for a...
- Patent number 10,395,698
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC MULTI-LANE DEGRADE CAPABILITY TO FACILITATE UNINTERRUPTED S...
- Publication number 20240311260
- Publication date Sep 19, 2024
- International Business Machines Corporation
- Rajat Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Decoder Providing Optimized Error Detection and Correction f...
- Publication number 20240103967
- Publication date Mar 28, 2024
- International Business Machines Corporation
- Barry M. Trager
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CABLE PAIR CONCURRENT SERVICING
- Publication number 20230393999
- Publication date Dec 7, 2023
- International Business Machines Corporation
- Rajat Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY DESERIALIZER HAVING FINE GRANULARITY AND DEFECTIVE-LANE...
- Publication number 20230115533
- Publication date Apr 13, 2023
- International Business Machines Corporation
- Patrick James Meaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-LATENCY, HIGH-AVAILABILITY AND HIGH-SPEED SERDES INTERFACE HAVI...
- Publication number 20230098514
- Publication date Mar 30, 2023
- International Business Machines Corporation
- Patrick James Meaney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW LATENCY AVAILABILITY IN DEGRADED REDUNDANT ARRAY OF INDEPENDENT...
- Publication number 20210406126
- Publication date Dec 30, 2021
- International Business Machines Corporation
- PATRICK JAMES MEANEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFRESH-HIDING MEMORY SYSTEM STAGGERED REFRESH
- Publication number 20210216401
- Publication date Jul 15, 2021
- International Business Machines Corporation
- PATRICK JAMES MEANEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY AVAILABILITY IN DEGRADED REDUNDANT ARRAY OF INDEPENDENT...
- Publication number 20210216400
- Publication date Jul 15, 2021
- International Business Machines Corporation
- PATRICK JAMES MEANEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...
- Publication number 20210191630
- Publication date Jun 24, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...
- Publication number 20200119843
- Publication date Apr 16, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC
- Publication number 20200097359
- Publication date Mar 26, 2020
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DIST...
- Publication number 20200073565
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...
- Publication number 20200042205
- Publication date Feb 6, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC
- Publication number 20190317856
- Publication date Oct 17, 2019
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for a...
- Publication number 20190252010
- Publication date Aug 15, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY
- Publication number 20190243709
- Publication date Aug 8, 2019
- International Business Machines Corporation
- Patrick J. MEANEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register Access in a Distributed Memory Buffer System
- Publication number 20190227741
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTION POTENCY IMPROVEMENT VIA ADDED BURST BEATS IN A DRA...
- Publication number 20190188074
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY
- Publication number 20190163565
- Publication date May 30, 2019
- International Business Machines Corporation
- Patrick J. MEANEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Host Controlled Data Chip Address Sequencing for a Distributed Memo...
- Publication number 20190163362
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Synchronized Autonomous Data Chip Address Sequ...
- Publication number 20190163378
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Host Synchronized Autonomous Data Chip Address Sequencer for A Dist...
- Publication number 20190163384
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for A...
- Publication number 20190163383
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE TYPES
- Publication number 20190158125
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE RATES
- Publication number 20190158218
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...
- Publication number 20190158223
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
USE OF MULTIPLE CYCLIC REDUNDANCY CODES FOR OPTIMIZED FAIL ISOLATION
- Publication number 20190158126
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PARTIAL DATA REPLAY IN A DISTRIBUTED MEMORY BUFFER SYSTEM
- Publication number 20190114091
- Publication date Apr 18, 2019
- International Business Machines Corporation
- Susan M. Eickhoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MIRROR INVOCATION UPON DETECTING A CORRECTABLE ERROR
- Publication number 20190079840
- Publication date Mar 14, 2019
- International Business Machines Corporation
- Marc A. Gollub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC TIME-DOMAIN REFLECTOMETRY ANALYSIS FOR FIELD REPLACEABLE UN...
- Publication number 20190020565
- Publication date Jan 17, 2019
- International Business Machines Corporation
- Luiz C. Alves
- G06 - COMPUTING CALCULATING COUNTING

Patrick J. Meaney

Person

Patents Grantslast 30 patents

Cable pair concurrent servicing

Low-latency deserializer having fine granularity and defective-lane...

Host synchronized autonomous data chip address sequencer for a dist...

Low-latency, high-availability and high-speed SerDes interface havi...

Low latency availability in degraded redundant array of independent...

Address/command chip controlled data chip address sequencing for a...

Refresh-hiding memory system staggered refresh

Address/command chip synchronized autonomous data chip address sequ...

Low latency availability in degraded redundant array of independent...

Use of a cyclic redundancy code multiple-input shift register to pr...

Address/command chip synchronized autonomous data chip address sequ...

Common high and low random bit error correction logic

Common high and low random bit error correction logic

High efficiency redundant array of independent memory

Host controlled data chip address sequencing for a distributed memo...

Conditional memory spreading for heterogeneous memory sizes

Dynamic time-domain reflectometry analysis for field replaceable un...

Dynamic time-domain reflectometry analysis for field replaceable un...

Register access in a distributed memory buffer system

Memory mirror invocation upon detecting a correctable error

Error correction potency improvement via added burst beats in a dra...

Reduced latency error correction decoding

Power-reduced redundant array of independent memory (RAIM) system

Use of a cyclic redundancy code multiple-input shift register to pr...

Host synchronized autonomous data chip address sequencer for a dist...

Dynamically adjustable cyclic redundancy code types

Dynamically adjustable cyclic redundancy code rates

Address/command chip synchronized autonomous data chip address sequ...

Use of multiple cyclic redundancy codes for optimized fail isolation

Address/command chip controlled data chip address sequencing for a...

Patents Applicationslast 30 patents

DYNAMIC MULTI-LANE DEGRADE CAPABILITY TO FACILITATE UNINTERRUPTED S...

Memory Decoder Providing Optimized Error Detection and Correction f...

CABLE PAIR CONCURRENT SERVICING

LOW-LATENCY DESERIALIZER HAVING FINE GRANULARITY AND DEFECTIVE-LANE...

LOW-LATENCY, HIGH-AVAILABILITY AND HIGH-SPEED SERDES INTERFACE HAVI...

LOW LATENCY AVAILABILITY IN DEGRADED REDUNDANT ARRAY OF INDEPENDENT...

REFRESH-HIDING MEMORY SYSTEM STAGGERED REFRESH

LOW LATENCY AVAILABILITY IN DEGRADED REDUNDANT ARRAY OF INDEPENDENT...

ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...

USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...

COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC

HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DIST...

ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...

COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC

Address/Command Chip Controlled Data Chip Address Sequencing for a...

HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY

Register Access in a Distributed Memory Buffer System

ERROR CORRECTION POTENCY IMPROVEMENT VIA ADDED BURST BEATS IN A DRA...

HIGH EFFICIENCY REDUNDANT ARRAY OF INDEPENDENT MEMORY

Host Controlled Data Chip Address Sequencing for a Distributed Memo...

Address/Command Chip Synchronized Autonomous Data Chip Address Sequ...

Host Synchronized Autonomous Data Chip Address Sequencer for A Dist...

Address/Command Chip Controlled Data Chip Address Sequencing for A...

DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE TYPES

DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE RATES

USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...

USE OF MULTIPLE CYCLIC REDUNDANCY CODES FOR OPTIMIZED FAIL ISOLATION

PARTIAL DATA REPLAY IN A DISTRIBUTED MEMORY BUFFER SYSTEM

MEMORY MIRROR INVOCATION UPON DETECTING A CORRECTABLE ERROR

DYNAMIC TIME-DOMAIN REFLECTOMETRY ANALYSIS FOR FIELD REPLACEABLE UN...