Patrick K. Cheung

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self aligned memory element and wordline
- Patent number 7,645,632
- Issue date Jan 12, 2010
- Spansion LLC
- Patrick K. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned memory element and wordline
- Patent number 7,220,985
- Issue date May 22, 2007
- Spansion, LLC
- Patrick K. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall formation for high density polymer memory element array
- Patent number 7,015,504
- Issue date Mar 21, 2006
- Advanced Micro Devices, Inc.
- Christopher F. Lyons
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory cell with UV protective layer
- Patent number 6,989,563
- Issue date Jan 24, 2006
- Advanced Micro Devices, Inc.
- Krishnashree Achuthan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory element formation with photosensitive polymer dielectric
- Patent number 6,955,939
- Issue date Oct 18, 2005
- Advanced Micro Devices, Inc.
- Christopher F. Lyons
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-cell organic memory element and methods of operating and fabr...
- Patent number 6,900,488
- Issue date May 31, 2005
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of forming a passive layer by a CMP process
- Patent number 6,836,398
- Issue date Dec 28, 2004
- Advanced Micro Devices, Inc.
- Ramkumar Subramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Silicon containing material for patterning polymeric memory element
- Patent number 6,803,267
- Issue date Oct 12, 2004
- Advanced Micro Devices, Inc.
- Ramkumar Subramanian
- G11 - INFORMATION STORAGE
Information Patent Grant
Polymer memory device formed in via opening
- Patent number 6,787,458
- Issue date Sep 7, 2004
- Advanced Micro Devices, Inc.
- Nicholas H. Tripsas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified graded LDD transistor using controlled polysilicon gate...
- Patent number 6,350,639
- Issue date Feb 26, 2002
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating graded LDD transistor using controlled polys...
- Patent number 6,287,922
- Issue date Sep 11, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified graded LDD transistor using controlled polysilicon gate...
- Patent number 6,274,443
- Issue date Aug 14, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming graded LDD transistor using controlled polysilic...
- Patent number 6,191,044
- Issue date Feb 20, 2001
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDD transistor using novel gate trim technique
- Patent number 6,013,570
- Issue date Jan 11, 2000
- Advanced Micro Devices, Inc.
- Allen S. Yu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF ALIGNED MEMORY ELEMENT AND WORDLINE
- Publication number 20070224724
- Publication date Sep 27, 2007
- SPANSION LLC
- Patrick K. Cheung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Sidewall formation for high density polymer memory element array
- Publication number 20050092983
- Publication date May 5, 2005
- Christopher F. Lyons
- G11 - INFORMATION STORAGE
Information Patent Application
Self aligned memory element and wordline
- Publication number 20040108501
- Publication date Jun 10, 2004
- Patrick K. Cheung
- H01 - BASIC ELECTRIC ELEMENTS

Patrick K. Cheung

Person

Patents Grantslast 30 patents

Self aligned memory element and wordline

Self aligned memory element and wordline

Sidewall formation for high density polymer memory element array

Flash memory cell with UV protective layer

Memory element formation with photosensitive polymer dielectric

Multi-cell organic memory element and methods of operating and fabr...

System and method of forming a passive layer by a CMP process

Silicon containing material for patterning polymeric memory element

Polymer memory device formed in via opening

Simplified graded LDD transistor using controlled polysilicon gate...

Method for fabricating graded LDD transistor using controlled polys...

Simplified graded LDD transistor using controlled polysilicon gate...

Method for forming graded LDD transistor using controlled polysilic...

LDD transistor using novel gate trim technique

Patents Applicationslast 30 patents

SELF ALIGNED MEMORY ELEMENT AND WORDLINE

Sidewall formation for high density polymer memory element array

Self aligned memory element and wordline