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Patrick M. Gannon
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Poughkeepsie, NY, US
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last 30 patents
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Patent Grant
Apparatus and method for TLB purge reduction in a multi-level machi...
Patent number
5,317,705
Issue date
May 31, 1994
International Business Machines Corporation
Patrick M. Gannon
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Coherence control by data invalidation in selected processor caches...
Patent number
5,265,232
Issue date
Nov 23, 1993
International Business Machines Corporation
Patrick M. Gannon
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Fast two-level dynamic address translation method and means
Patent number
4,695,950
Issue date
Sep 22, 1987
International Business Machines Corporation
Henry R. Brandt
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Cache bypass control for operand fetches
Patent number
4,189,770
Issue date
Feb 19, 1980
International Business Machines Corporation
Patrick M. Gannon
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Technique for performing partial stores in store-thru memory config...
Patent number
4,157,586
Issue date
Jun 5, 1979
International Business Machines Corporation
Patrick M. Gannon
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
High speed store request processing control
Patent number
4,149,245
Issue date
Apr 10, 1979
International Business Machines Corporation
Patrick M. Gannon
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Synonym control means for multiple virtual storage systems
Patent number
4,136,385
Issue date
Jan 23, 1979
International Business Machines Corporation
Patrick M. Gannon
G06 - COMPUTING CALCULATING COUNTING