Patrick Vuillod

Person

St. Bernard du Touvet, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Fast synthesis of logical circuit design with predictive timing
- Patent number 12,175,176
- Issue date Dec 24, 2024
- Synopsys, Inc.
- Peter Moceyunas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Satisfiability sweeping for synthesis
- Patent number 11,120,184
- Issue date Sep 14, 2021
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable boolean methods in a modern synthesis flow
- Patent number 11,010,511
- Issue date May 18, 2021
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Robust exclusive sum-of-product (ESOP) refactoring
- Patent number 10,839,117
- Issue date Nov 17, 2020
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit (IC) optimization using Boolean resynthesis
- Patent number 10,740,517
- Issue date Aug 11, 2020
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exact delay synthesis
- Patent number 10,325,051
- Issue date Jun 18, 2019
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Exact delay synthesis
- Patent number 10,049,174
- Issue date Aug 14, 2018
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay optimization during circuit design at layout level
- Patent number 8,549,448
- Issue date Oct 1, 2013
- Synopsys, Inc.
- Patrick Vuillod
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT DESIGN ADJUSTMENTS USING REDUNDANT NODES
- Publication number 20240078366
- Publication date Mar 7, 2024
- Synopsys, Inc.
- Eleonora TESTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFIABILITY-BASED RESUBSTITUTION FOR INCREMENTAL MAPPED OPTIMIZA...
- Publication number 20230351082
- Publication date Nov 2, 2023
- Synopsys, Inc.
- Vinicius NEVES POSSANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST SYNTHESIS OF LOGICAL CIRCUIT DESIGN WITH PREDICTIVE TIMING
- Publication number 20220300688
- Publication date Sep 22, 2022
- Synopsys, Inc.
- Peter Moceyunas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SATISFIABILITY SWEEPING FOR SYNTHESIS
- Publication number 20200394352
- Publication date Dec 17, 2020
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE BOOLEAN METHODS IN A MODERN SYNTHESIS FLOW
- Publication number 20200074019
- Publication date Mar 5, 2020
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXACT DELAY SYNTHESIS
- Publication number 20180239846
- Publication date Aug 23, 2018
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXACT DELAY SYNTHESIS
- Publication number 20180173818
- Publication date Jun 21, 2018
- Synopsys, Inc.
- Luca Gaetano Amaru
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method of Delay Optimization
- Publication number 20110010680
- Publication date Jan 13, 2011
- Synopsys, Inc.
- Patrick Vuillod
- G06 - COMPUTING CALCULATING COUNTING

Patrick Vuillod

Person

Patents Grantslast 30 patents

Fast synthesis of logical circuit design with predictive timing

Satisfiability sweeping for synthesis

Scalable boolean methods in a modern synthesis flow

Robust exclusive sum-of-product (ESOP) refactoring

Integrated circuit (IC) optimization using Boolean resynthesis

Exact delay synthesis

Exact delay synthesis

Delay optimization during circuit design at layout level

Patents Applicationslast 30 patents

CIRCUIT DESIGN ADJUSTMENTS USING REDUNDANT NODES

SATISFIABILITY-BASED RESUBSTITUTION FOR INCREMENTAL MAPPED OPTIMIZA...

FAST SYNTHESIS OF LOGICAL CIRCUIT DESIGN WITH PREDICTIVE TIMING

SATISFIABILITY SWEEPING FOR SYNTHESIS

SCALABLE BOOLEAN METHODS IN A MODERN SYNTHESIS FLOW

EXACT DELAY SYNTHESIS

EXACT DELAY SYNTHESIS

Apparatus and Method of Delay Optimization