Paul A. Merolla

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Neuromorphic event-driven neural computing architecture in a scalab...
- Patent number 11,580,366
- Issue date Feb 14, 2023
- International Business Machines Corporation
- Filipp Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware architecture for simulating a neural network of neurons
- Patent number 11,341,401
- Issue date May 24, 2022
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-division multiplexed neurosynaptic module with implicit memory...
- Patent number 11,295,201
- Issue date Apr 5, 2022
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable neural hardware for the noisy-OR model of Bayesian networks
- Patent number 11,238,343
- Issue date Feb 1, 2022
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Yield tolerance in a neurosynaptic system
- Patent number 11,184,221
- Issue date Nov 23, 2021
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing transposable access to a synapse array using a recursive...
- Patent number 11,074,496
- Issue date Jul 27, 2021
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event-based neural network with hierarchical addressing for routing...
- Patent number 11,049,001
- Issue date Jun 29, 2021
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-efficient time-multiplexed neurosynaptic core for implementi...
- Patent number 10,990,872
- Issue date Apr 27, 2021
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping graphs onto core-based neuromorphic architectures
- Patent number 10,984,312
- Issue date Apr 20, 2021
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral device interconnections for neurosynaptic systems
- Patent number 10,984,307
- Issue date Apr 20, 2021
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual deterministic and stochastic neurosynaptic core circuit
- Patent number 10,929,747
- Issue date Feb 23, 2021
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-mapped interface to message-passing computing systems
- Patent number 10,838,860
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Globally asynchronous and locally synchronous (GALS) neuromorphic n...
- Patent number 10,839,287
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing a neural network algorithm on a neurosynaptic substrat...
- Patent number 10,832,125
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scaling multi-core neurosynaptic networks across chip boundaries
- Patent number 10,785,745
- Issue date Sep 22, 2020
- International Business Machines Corporation
- Rodrigo Alvarez Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting digital numeric data to spike event data
- Patent number 10,769,519
- Issue date Sep 8, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Converting spike event data to digital numeric data
- Patent number 10,755,165
- Issue date Aug 25, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect circuits at three-dimensional (3-D) bonding interfaces...
- Patent number 10,740,282
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplexing physical neurons to optimize power and area
- Patent number 10,713,561
- Issue date Jul 14, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing a distributed and parallel set of neurosynaptic core circ...
- Patent number 10,650,301
- Issue date May 12, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neuromorphic event-driven neural computing architecture in a scalab...
- Patent number 10,504,021
- Issue date Dec 10, 2019
- International Business Machines Corporation
- Filipp Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Yield tolerance in a neurosynaptic system
- Patent number 10,454,759
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Rodrigo Alvarez Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-mapped interface for message passing computing systems
- Patent number 10,452,540
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Peripheral device interconnections for neurosynaptic systems
- Patent number 10,410,109
- Issue date Sep 10, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Time-division multiplexed neurosynaptic module with implicit memory...
- Patent number 10,331,998
- Issue date Jun 25, 2019
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware architecture for simulating a neural network of neurons
- Patent number 10,282,658
- Issue date May 7, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping neural dynamics of a neural model on to a coarsely grained...
- Patent number 10,204,118
- Issue date Feb 12, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing a neural network algorithm on a neurosynaptic substrat...
- Patent number 10,204,301
- Issue date Feb 12, 2019
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable neural hardware for the noisy-OR model of Bayesian networks
- Patent number 10,198,692
- Issue date Feb 5, 2019
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Faulty core recovery mechanisms for a three-dimensional network on...
- Patent number 10,176,063
- Issue date Jan 8, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING FOR ROUTING...
- Publication number 20210166107
- Publication date Jun 3, 2021
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...
- Publication number 20200364535
- Publication date Nov 19, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEUROMORPHIC EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN A SCALAB...
- Publication number 20200065658
- Publication date Feb 27, 2020
- International Business Machines Corporation
- Filipp Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-MAPPED INTERFACE TO MESSAGE-PASSING COMPUTING SYSTEMS
- Publication number 20200004678
- Publication date Jan 2, 2020
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM
- Publication number 20190372831
- Publication date Dec 5, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERIPHERAL DEVICE INTERCONNECTIONS FOR NEUROSYNAPTIC SYSTEMS
- Publication number 20190294950
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...
- Publication number 20190228289
- Publication date Jul 25, 2019
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS
- Publication number 20190197394
- Publication date Jun 27, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE NEURAL HARDWARE FOR THE NOISY-OR MODEL OF BAYESIAN NETWORKS
- Publication number 20190156209
- Publication date May 23, 2019
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-MAPPED INTERFACE FOR MESSAGE PASSING COMPUTING SYSTEMS
- Publication number 20190121734
- Publication date Apr 25, 2019
- International Business Machines Corporation
- Filipp A. Akopyan
- G11 - INFORMATION STORAGE
Information Patent Application
YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM
- Publication number 20180287862
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL DETERMINISTIC AND STOCHASTIC NEUROSYNAPTIC CORE CIRCUIT
- Publication number 20180232634
- Publication date Aug 16, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...
- Publication number 20180211163
- Publication date Jul 26, 2018
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20180189233
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING A NEURAL NETWORK ALGORITHM ON A NEUROSYNAPTIC SUBSTRAT...
- Publication number 20180189637
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING NEURAL DYNAMICS OF A NEURAL MODEL ON TO A COARSELY GRAINED...
- Publication number 20180113885
- Publication date Apr 26, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALING MULTI-CORE NEUROSYNAPTIC NETWORKS ACROSS CHIP BOUNDARIES
- Publication number 20180103448
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING SPIKE EVENT DATA TO DIGITAL NUMERIC DATA
- Publication number 20180082174
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERTING DIGITAL NUMERIC DATA TO SPIKE EVENT DATA
- Publication number 20180082173
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING GRAPHS ONTO CORE-BASED NEUROMORPHIC ARCHITECTURES
- Publication number 20180075340
- Publication date Mar 15, 2018
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY-EFFICIENT TIME-MULTIPLEXED NEUROSYNAPTIC CORE FOR IMPLEMENTI...
- Publication number 20170286825
- Publication date Oct 5, 2017
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INITIALIZING AND TESTING INTEGRATED CIRCUITS WITH SELECTABLE SCAN C...
- Publication number 20170199241
- Publication date Jul 13, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G01 - MEASURING TESTING
Information Patent Application
ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS
- Publication number 20170124024
- Publication date May 4, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...
- Publication number 20170076197
- Publication date Mar 16, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL DETERMINISTIC AND STOCHASTIC NEUROSYNAPTIC CORE CIRCUIT
- Publication number 20170068885
- Publication date Mar 9, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS
- Publication number 20160358066
- Publication date Dec 8, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING A NEURAL NETWORK ALGORITHM ON A NEUROSYNAPTIC SUBSTRAT...
- Publication number 20160335535
- Publication date Nov 17, 2016
- International Business Machines Corporation
- Arnon Amir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM
- Publication number 20160323137
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING
- Publication number 20160321539
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSOLIDATING MULTIPLE NEUROSYNAPTIC CORE CIRCUITS INTO ONE RECONFI...
- Publication number 20160321537
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Filipp A. Akopyan
- G06 - COMPUTING CALCULATING COUNTING

Paul A. Merolla

Person

Patents Grantslast 30 patents

Neuromorphic event-driven neural computing architecture in a scalab...

Hardware architecture for simulating a neural network of neurons

Time-division multiplexed neurosynaptic module with implicit memory...

Scalable neural hardware for the noisy-OR model of Bayesian networks

Yield tolerance in a neurosynaptic system

Providing transposable access to a synapse array using a recursive...

Event-based neural network with hierarchical addressing for routing...

Energy-efficient time-multiplexed neurosynaptic core for implementi...

Mapping graphs onto core-based neuromorphic architectures

Peripheral device interconnections for neurosynaptic systems

Dual deterministic and stochastic neurosynaptic core circuit

Memory-mapped interface to message-passing computing systems

Globally asynchronous and locally synchronous (GALS) neuromorphic n...

Implementing a neural network algorithm on a neurosynaptic substrat...

Scaling multi-core neurosynaptic networks across chip boundaries

Converting digital numeric data to spike event data

Converting spike event data to digital numeric data

Interconnect circuits at three-dimensional (3-D) bonding interfaces...

Multiplexing physical neurons to optimize power and area

Utilizing a distributed and parallel set of neurosynaptic core circ...

Neuromorphic event-driven neural computing architecture in a scalab...

Yield tolerance in a neurosynaptic system

Memory-mapped interface for message passing computing systems

Peripheral device interconnections for neurosynaptic systems

Time-division multiplexed neurosynaptic module with implicit memory...

Hardware architecture for simulating a neural network of neurons

Mapping neural dynamics of a neural model on to a coarsely grained...

Implementing a neural network algorithm on a neurosynaptic substrat...

Scalable neural hardware for the noisy-OR model of Bayesian networks

Faulty core recovery mechanisms for a three-dimensional network on...

Patents Applicationslast 30 patents

EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING FOR ROUTING...

GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...

NEUROMORPHIC EVENT-DRIVEN NEURAL COMPUTING ARCHITECTURE IN A SCALAB...

MEMORY-MAPPED INTERFACE TO MESSAGE-PASSING COMPUTING SYSTEMS

YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM

PERIPHERAL DEVICE INTERCONNECTIONS FOR NEUROSYNAPTIC SYSTEMS

TIME-DIVISION MULTIPLEXED NEUROSYNAPTIC MODULE WITH IMPLICIT MEMORY...

HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS

SCALABLE NEURAL HARDWARE FOR THE NOISY-OR MODEL OF BAYESIAN NETWORKS

MEMORY-MAPPED INTERFACE FOR MESSAGE PASSING COMPUTING SYSTEMS

YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM

DUAL DETERMINISTIC AND STOCHASTIC NEUROSYNAPTIC CORE CIRCUIT

PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...

IMPLEMENTING A NEURAL NETWORK ALGORITHM ON A NEUROSYNAPTIC SUBSTRAT...

MAPPING NEURAL DYNAMICS OF A NEURAL MODEL ON TO A COARSELY GRAINED...

SCALING MULTI-CORE NEUROSYNAPTIC NETWORKS ACROSS CHIP BOUNDARIES

CONVERTING SPIKE EVENT DATA TO DIGITAL NUMERIC DATA

CONVERTING DIGITAL NUMERIC DATA TO SPIKE EVENT DATA

MAPPING GRAPHS ONTO CORE-BASED NEUROMORPHIC ARCHITECTURES

ENERGY-EFFICIENT TIME-MULTIPLEXED NEUROSYNAPTIC CORE FOR IMPLEMENTI...

INITIALIZING AND TESTING INTEGRATED CIRCUITS WITH SELECTABLE SCAN C...

ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS

GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS) NEUROMORPHIC N...

DUAL DETERMINISTIC AND STOCHASTIC NEUROSYNAPTIC CORE CIRCUIT

HARDWARE ARCHITECTURE FOR SIMULATING A NEURAL NETWORK OF NEURONS

IMPLEMENTING A NEURAL NETWORK ALGORITHM ON A NEUROSYNAPTIC SUBSTRAT...

YIELD TOLERANCE IN A NEUROSYNAPTIC SYSTEM

EVENT-BASED NEURAL NETWORK WITH HIERARCHICAL ADDRESSING

CONSOLIDATING MULTIPLE NEUROSYNAPTIC CORE CIRCUITS INTO ONE RECONFI...