Paul A. Nyhus

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self aligned gratings for tight pitch interconnects and methods of...
- Patent number 12,131,991
- Issue date Oct 29, 2024
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical metal splitting using helmets and wrap-around dielectric s...
- Patent number 12,131,989
- Issue date Oct 29, 2024
- Intel Corporation
- Leonard P. Guler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Colored gratings in microelectronic structures
- Patent number 12,087,594
- Issue date Sep 10, 2024
- Intel Corporation
- Gurpreet Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact over active gate structures with metal oxide layers to inhi...
- Patent number 12,080,639
- Issue date Sep 3, 2024
- Intel Corporation
- Rami Hourani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate spacing in integrated circuit structures
- Patent number 12,002,678
- Issue date Jun 4, 2024
- Intel Corporation
- Charles Henry Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,972,979
- Issue date Apr 30, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 11,854,787
- Issue date Dec 26, 2023
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,721,580
- Issue date Aug 8, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Materials and layout design options for DSA on transition regions o...
- Patent number 11,605,623
- Issue date Mar 14, 2023
- Intel Corporation
- Gurpreet Singh
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Grant
Vertical edge blocking (VEB) technique for increasing patterning pr...
- Patent number 11,594,448
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guard ring structure for an integrated circuit
- Patent number 11,545,449
- Issue date Jan 3, 2023
- Intel Corporation
- Paul A. Nyhus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via and plug architectures for integrated circuit interconnects and...
- Patent number 11,527,433
- Issue date Dec 13, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive cap-based approaches for conductive via fabrication and...
- Patent number 11,417,567
- Issue date Aug 16, 2022
- Intel Corporation
- Florian Gstrein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 11,373,950
- Issue date Jun 28, 2022
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self aligned gratings for tight pitch interconnects and methods of...
- Patent number 11,251,117
- Issue date Feb 15, 2022
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned via and plug patterning for back end of line (BEOL) in...
- Patent number 10,991,599
- Issue date Apr 27, 2021
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced lithography and self-assembled devices
- Patent number 10,892,223
- Issue date Jan 12, 2021
- Intel Corporation
- Richard E. Schenker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Means to decouple the diffusion and solubility switch mechanisms of...
- Patent number 10,692,757
- Issue date Jun 23, 2020
- Intel Corporation
- Marie Krysak
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Grant
Metal via processing schemes with via critical dimension (CD) contr...
- Patent number 10,636,700
- Issue date Apr 28, 2020
- Intel Corporation
- Paul A. Nyhus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned isotropic etch of pre-formed vias and plugs for back e...
- Patent number 10,600,678
- Issue date Mar 24, 2020
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pitch division patterning approaches with increased overlay margin...
- Patent number 10,559,529
- Issue date Feb 11, 2020
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Exposure activated chemically amplified directed self-assembly (DSA...
- Patent number 10,459,338
- Issue date Oct 29, 2019
- Intel Corporation
- Paul A. Nyhus
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Underlying absorbing or conducting layer for Ebeam direct write (EB...
- Patent number 10,338,474
- Issue date Jul 2, 2019
- Intel Corporation
- Shakul Tandon
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Patterning of vertical nanowire transistor channel and gate with di...
- Patent number 10,325,814
- Issue date Jun 18, 2019
- Intel Corporation
- Paul A. Nyhus
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Metal via processing schemes with via critical dimension (CD) contr...
- Patent number 10,319,625
- Issue date Jun 11, 2019
- Intel Corporation
- Paul A. Nyhus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned via and plug patterning for back end of line (BEOL) in...
- Patent number 10,297,467
- Issue date May 21, 2019
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned isotropic etch of pre-formed vias and plugs for back e...
- Patent number 10,211,088
- Issue date Feb 19, 2019
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Previous layer self-aligned via and plug patterning for back end of...
- Patent number 10,204,830
- Issue date Feb 12, 2019
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Previous layer self-aligned via and plug patterning for back end of...
- Patent number 9,793,159
- Issue date Oct 17, 2017
- Intel Corporation
- Charles H. Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Subtractive self-aligned via and plug patterning for back end of li...
- Patent number 9,793,163
- Issue date Oct 17, 2017
- Intel Corporation
- Robert L. Bristol
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC S...
- Publication number 20250029915
- Publication date Jan 23, 2025
- Intel Corporation
- Leonard P. Guler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES
- Publication number 20240249946
- Publication date Jul 25, 2024
- Intel Corporation
- Charles Henry Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES
- Publication number 20240071917
- Publication date Feb 29, 2024
- Intel Corporation
- Richard E. SCHENKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG
- Publication number 20230326794
- Publication date Oct 12, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT E...
- Publication number 20230307298
- Publication date Sep 28, 2023
- Intel Corporation
- Charles H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL EDGE BLOCKING (VEB) TECHNIQUE FOR INCREASING PATTERNING PR...
- Publication number 20230145089
- Publication date May 11, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE TRENCH CONTACT...
- Publication number 20230095402
- Publication date Mar 30, 2023
- Intel Corporation
- Manish CHANDHOK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE TRENCH CONTACT...
- Publication number 20230101212
- Publication date Mar 30, 2023
- Intel Corporation
- Manish CHANDHOK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES
- Publication number 20220262722
- Publication date Aug 18, 2022
- Intel Corporation
- Richard E. SCHENKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COLORED GRATINGS IN MICROELECTRONIC STRUCTURES
- Publication number 20220199420
- Publication date Jun 23, 2022
- Intel Corporation
- Gurpreet Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF ALIGNED GRATINGS FOR TIGHT PITCH INTERCONNECTS AND METHODS OF...
- Publication number 20220173034
- Publication date Jun 2, 2022
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC S...
- Publication number 20220157708
- Publication date May 19, 2022
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES
- Publication number 20220102148
- Publication date Mar 31, 2022
- Intel Corporation
- Charles Henry Wallace
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT OVER ACTIVE GATE STRUCTURES USING DIRECTED SELF-ASSEMBLY FO...
- Publication number 20220102210
- Publication date Mar 31, 2022
- Intel Corporation
- Paul A. NYHUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA & PLUG ARCHITECTURES FOR INTEGRATED CIRCUIT INTERCONNECTS & MET...
- Publication number 20210313222
- Publication date Oct 7, 2021
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT OVER ACTIVE GATE STRUCTURES WITH METAL OXIDE LAYERS TO INHI...
- Publication number 20210090990
- Publication date Mar 25, 2021
- Intel Corporation
- Rami HOURANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES
- Publication number 20210082800
- Publication date Mar 18, 2021
- Intel Corporation
- Richard E. SCHENKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF ALIGNED GRATINGS FOR TIGHT PITCH INTERCONNECTS AND METHODS OF...
- Publication number 20210074632
- Publication date Mar 11, 2021
- Intel Corporation
- Manish Chandhok
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MATERIALS AND LAYOUT DESIGN OPTIONS FOR DSA ON TRANSITION REGIONS O...
- Publication number 20200411501
- Publication date Dec 31, 2020
- Intel Corporation
- Gurpreet SINGH
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Application
VERTICAL EDGE BLOCKING (VEB) TECHNIQUE FOR INCREASING PATTERNING PR...
- Publication number 20200388530
- Publication date Dec 10, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG
- Publication number 20200388534
- Publication date Dec 10, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES
- Publication number 20200066629
- Publication date Feb 27, 2020
- Intel Corporation
- Richard E. SCHENKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GUARD RING STRUCTURE FOR AN INTEGRATED CIRCUIT
- Publication number 20190393170
- Publication date Dec 26, 2019
- Intel Corporation
- Paul A. Nyhus
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CAP-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND...
- Publication number 20190363008
- Publication date Nov 28, 2019
- Intel Corporation
- Florian GSTREIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL VIA PROCESSING SCHEMES WITH VIA CRITICAL DIMENSION (CD) CONTR...
- Publication number 20190259656
- Publication date Aug 22, 2019
- Intel Corporation
- Paul A. NYHUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED VIA AND PLUG PATTERNING FOR BACK END OF LINE (BEOL) IN...
- Publication number 20190252208
- Publication date Aug 15, 2019
- Intel Corporation
- CHARLES H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED ISOTROPIC ETCH OF PRE-FORMED VIAS AND PLUGS FOR BACK E...
- Publication number 20190148220
- Publication date May 16, 2019
- Intel Corporation
- CHARLES H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PITCH DIVISION PATTERNING APPROACHES WITH INCREASED OVERLAY MARGIN...
- Publication number 20190019748
- Publication date Jan 17, 2019
- Intel Corporation
- Charles H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT E...
- Publication number 20190013246
- Publication date Jan 10, 2019
- Intel Corporation
- Charles H. WALLACE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PITCH DIVISION USING DIRECTED SELF-ASSEMBLY
- Publication number 20180323078
- Publication date Nov 8, 2018
- Intel Corporation
- Stephanie A. BOJARSKI
- H01 - BASIC ELECTRIC ELEMENTS

Paul A. Nyhus

Person

Patents Grantslast 30 patents

Self aligned gratings for tight pitch interconnects and methods of...

Vertical metal splitting using helmets and wrap-around dielectric s...

Colored gratings in microelectronic structures

Contact over active gate structures with metal oxide layers to inhi...

Gate spacing in integrated circuit structures

1D vertical edge blocking (VEB) via and plug

Advanced lithography and self-assembled devices

1D vertical edge blocking (VEB) via and plug

Materials and layout design options for DSA on transition regions o...

Vertical edge blocking (VEB) technique for increasing patterning pr...

Guard ring structure for an integrated circuit

Via and plug architectures for integrated circuit interconnects and...

Conductive cap-based approaches for conductive via fabrication and...

Advanced lithography and self-assembled devices

Self aligned gratings for tight pitch interconnects and methods of...

Self-aligned via and plug patterning for back end of line (BEOL) in...

Advanced lithography and self-assembled devices

Means to decouple the diffusion and solubility switch mechanisms of...

Metal via processing schemes with via critical dimension (CD) contr...

Self-aligned isotropic etch of pre-formed vias and plugs for back e...

Pitch division patterning approaches with increased overlay margin...

Exposure activated chemically amplified directed self-assembly (DSA...

Underlying absorbing or conducting layer for Ebeam direct write (EB...

Patterning of vertical nanowire transistor channel and gate with di...

Metal via processing schemes with via critical dimension (CD) contr...

Self-aligned via and plug patterning for back end of line (BEOL) in...

Self-aligned isotropic etch of pre-formed vias and plugs for back e...

Previous layer self-aligned via and plug patterning for back end of...

Previous layer self-aligned via and plug patterning for back end of...

Subtractive self-aligned via and plug patterning for back end of li...

Patents Applicationslast 30 patents

VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC S...

GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG

ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT E...

VERTICAL EDGE BLOCKING (VEB) TECHNIQUE FOR INCREASING PATTERNING PR...

CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE TRENCH CONTACT...

CONTACT OVER ACTIVE GATE STRUCTURES WITH CONDUCTIVE TRENCH CONTACT...

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

COLORED GRATINGS IN MICROELECTRONIC STRUCTURES

SELF ALIGNED GRATINGS FOR TIGHT PITCH INTERCONNECTS AND METHODS OF...

VERTICAL METAL SPLITTING USING HELMETS AND WRAP-AROUND DIELECTRIC S...

GATE SPACING IN INTEGRATED CIRCUIT STRUCTURES

CONTACT OVER ACTIVE GATE STRUCTURES USING DIRECTED SELF-ASSEMBLY FO...

VIA & PLUG ARCHITECTURES FOR INTEGRATED CIRCUIT INTERCONNECTS & MET...

CONTACT OVER ACTIVE GATE STRUCTURES WITH METAL OXIDE LAYERS TO INHI...

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

SELF ALIGNED GRATINGS FOR TIGHT PITCH INTERCONNECTS AND METHODS OF...

MATERIALS AND LAYOUT DESIGN OPTIONS FOR DSA ON TRANSITION REGIONS O...

VERTICAL EDGE BLOCKING (VEB) TECHNIQUE FOR INCREASING PATTERNING PR...

1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG

ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES

GUARD RING STRUCTURE FOR AN INTEGRATED CIRCUIT

CONDUCTIVE CAP-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND...

METAL VIA PROCESSING SCHEMES WITH VIA CRITICAL DIMENSION (CD) CONTR...

SELF-ALIGNED VIA AND PLUG PATTERNING FOR BACK END OF LINE (BEOL) IN...

SELF-ALIGNED ISOTROPIC ETCH OF PRE-FORMED VIAS AND PLUGS FOR BACK E...

PITCH DIVISION PATTERNING APPROACHES WITH INCREASED OVERLAY MARGIN...

ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT E...

PITCH DIVISION USING DIRECTED SELF-ASSEMBLY