Paul A. Reed

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for performing different cache replacement alg...
- Patent number 5,778,432
- Issue date Jul 7, 1998
- Motorola, Inc.
- Lawrence H. Rubin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processor with alocate bit and method of operation
- Patent number 5,765,199
- Issue date Jun 9, 1998
- Motorola, Inc.
- Joseph Y. Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cache with low power consumption and method of operation
- Patent number 5,550,774
- Issue date Aug 27, 1996
- Motorola, Inc.
- Michael L. Brauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory and associated method including an operating mode for simult...
- Patent number 5,367,655
- Issue date Nov 22, 1994
- Motorola, Inc.
- Anita S. Grossman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latching sense amplifier
- Patent number 5,294,847
- Issue date Mar 15, 1994
- Motorola, Inc.
- Anita S. Grossman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system for reliably writing addresses with reduced power con...
- Patent number 5,130,947
- Issue date Jul 14, 1992
- Motorola, Inc.
- Paul A. Reed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnostic mode for a cache
- Patent number 4,996,641
- Issue date Feb 26, 1991
- Motorola, Inc.
- Yoav Talgam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance output driver
- Patent number 4,716,550
- Issue date Dec 29, 1987
- Motorola, Inc.
- Stephen T. Flannagan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture with sub-arrays
- Patent number 4,698,788
- Issue date Oct 6, 1987
- Motorola, Inc.
- Stephen T. Flannagan
- G11 - INFORMATION STORAGE
Information Patent Grant
Asynchronous row and column control
- Patent number 4,661,931
- Issue date Apr 28, 1987
- Motorola, Inc.
- Stephen T. Flannagan
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line precharge on a column address change
- Patent number 4,658,381
- Issue date Apr 14, 1987
- Motorola, Inc.
- Paul A. Reed
- G11 - INFORMATION STORAGE
Information Patent Grant
Summation of address transition signals
- Patent number 4,636,991
- Issue date Jan 13, 1987
- Motorola, Inc.
- Stephen T. Flannagan
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip select speed-up circuit for a memory
- Patent number 4,630,239
- Issue date Dec 16, 1986
- Motorola, Inc.
- Paul A. Reed
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Transferring data from stacked memory
- Publication number 20070220207
- Publication date Sep 20, 2007
- Bryan Black
- G06 - COMPUTING CALCULATING COUNTING

Paul A. Reed

Person

Patents Grantslast 30 patents

Method and apparatus for performing different cache replacement alg...

Data processor with alocate bit and method of operation

Memory cache with low power consumption and method of operation

Memory and associated method including an operating mode for simult...

Latching sense amplifier

Memory system for reliably writing addresses with reduced power con...

Diagnostic mode for a cache

High performance output driver

Memory architecture with sub-arrays

Asynchronous row and column control

Bit line precharge on a column address change

Summation of address transition signals

Chip select speed-up circuit for a memory

Patents Applicationslast 30 patents

Transferring data from stacked memory