Paul Breuder

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,735,675
- Issue date May 11, 2004
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
External bus transaction scheduling system
- Patent number 6,732,242
- Issue date May 4, 2004
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,668,309
- Issue date Dec 23, 2003
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,578,116
- Issue date Jun 10, 2003
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,578,114
- Issue date Jun 10, 2003
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Snoop blocking for cache coherency
- Patent number 6,460,119
- Issue date Oct 1, 2002
- Intel Corporation
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for altering data length to zero to maintain c...
- Patent number 6,434,677
- Issue date Aug 13, 2002
- Intel Corporation
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction system in a processing agent having minimal delay
- Patent number 6,412,091
- Issue date Jun 25, 2002
- Intel Corporation
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
“SLIME” cache coherency system for agents with mult...
- Patent number 6,378,048
- Issue date Apr 23, 2002
- Intel Corporation
- Chinna Prudvi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction system in a processing agent having minimal delay
- Patent number 6,269,465
- Issue date Jul 31, 2001
- Intel Corporation
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transaction stall technique to prevent livelock in multiple-process...
- Patent number 6,078,981
- Issue date Jun 20, 2000
- Intel Corporation
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
External bus transaction scheduling system
- Publication number 20030188107
- Publication date Oct 2, 2003
- David L. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop blocking for cache coherency
- Publication number 20030115424
- Publication date Jun 19, 2003
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for altering data length to zero to maintain c...
- Publication number 20030110359
- Publication date Jun 12, 2003
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Snoop blocking for cache coherency
- Publication number 20020199068
- Publication date Dec 26, 2002
- Derek T. Bachand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for altering data length to zero to maintain c...
- Publication number 20020156982
- Publication date Oct 24, 2002
- Paul D. Breuder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error correction system in a processing agent having minimal delay
- Publication number 20010020286
- Publication date Sep 6, 2001
- David L. Hill
- H03 - BASIC ELECTRONIC CIRCUITRY

Paul Breuder

Person

Patents Grantslast 30 patents

Method and apparatus for altering data length to zero to maintain c...

External bus transaction scheduling system

Snoop blocking for cache coherency

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Error correction system in a processing agent having minimal delay

&#x0201C;SLIME&#x0201D; cache coherency system for agents with mult...

Error correction system in a processing agent having minimal delay

Transaction stall technique to prevent livelock in multiple-process...

Patents Applicationslast 30 patents

External bus transaction scheduling system

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Snoop blocking for cache coherency

Method and apparatus for altering data length to zero to maintain c...

Error correction system in a processing agent having minimal delay

“SLIME” cache coherency system for agents with mult...