Paul C. Rossbach

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Logic circuitry
- Patent number 7,221,188
- Issue date May 22, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Andrew A. Bjorksten
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data processing system having a synchronizing link stack and method...
- Patent number 6,157,999
- Issue date Dec 5, 2000
- Motorola Inc.
- Paul C. Rossbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system in data processing system of permitting concurren...
- Patent number 5,974,535
- Issue date Oct 26, 1999
- International Business Machines Corporation
- Chih-Jui Ray Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor having a selectively configurable branch prediction unit...
- Patent number 5,901,307
- Issue date May 4, 1999
- International Business Machines Corporation
- Terence Matthew Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system in a superscalar data processing system for the e...
- Patent number 5,784,606
- Issue date Jul 21, 1998
- International Business Machines Corporation
- Thomas Alan Hoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system in a data processing system for efficient managem...
- Patent number 5,765,017
- Issue date Jun 9, 1998
- International Business Machines Corporation
- Thomas Alan Hoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of addressing which minimize memory utilized to s...
- Patent number 5,765,221
- Issue date Jun 9, 1998
- International Business Machines Corporation
- Paul Charles Rossbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semi-associative cache with MRU/LRU replacement
- Patent number 5,715,427
- Issue date Feb 3, 1998
- International Business Machines Corporation
- David Daniel Barrera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processor with programmable levels of speculative instruction...
- Patent number 5,553,255
- Issue date Sep 3, 1996
- Motorola, Inc.
- Danny K. Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cache with automatic alliased entry invalidation and method...
- Patent number 5,550,995
- Issue date Aug 27, 1996
- Motorola, Inc.
- David D. Barrera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address translation circuit
- Patent number 5,530,824
- Issue date Jun 25, 1996
- Motorola, Inc.
- Chih-Jiu Peng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cache with interlaced data and method of operation
- Patent number 5,499,204
- Issue date Mar 12, 1996
- Motorola, Inc.
- David Barrera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoder/comparator and method of operation
- Patent number 5,291,076
- Issue date Mar 1, 1994
- Motorola, Inc.
- Jeffrey T. Bridges
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing integer and floating point divi...
- Patent number 5,272,660
- Issue date Dec 21, 1993
- Motorola, Inc.
- Paul C. Rossbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In a data processor an SRT divider having a negative divisor sticky...
- Patent number 5,237,525
- Issue date Aug 17, 1993
- Motorola, Inc.
- Paul C. Rossbach
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Logic circuitry
- Publication number 20060082388
- Publication date Apr 20, 2006
- Andrew A. Bjorksten
- H03 - BASIC ELECTRONIC CIRCUITRY

Paul C. Rossbach

Person

Patents Grantslast 30 patents

Logic circuitry

Data processing system having a synchronizing link stack and method...

Method and system in data processing system of permitting concurren...

Processor having a selectively configurable branch prediction unit...

Method and system in a superscalar data processing system for the e...

Method and system in a data processing system for efficient managem...

Method and system of addressing which minimize memory utilized to s...

Semi-associative cache with MRU/LRU replacement

Data processor with programmable levels of speculative instruction...

Memory cache with automatic alliased entry invalidation and method...

Address translation circuit

Memory cache with interlaced data and method of operation

Decoder/comparator and method of operation

Method and apparatus for performing integer and floating point divi...

In a data processor an SRT divider having a negative divisor sticky...

Patents Applicationslast 30 patents

Logic circuitry