Paul D. Madland

Person

Beverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method to control self-timed and synchronous systems
- Patent number 7,282,975
- Issue date Oct 16, 2007
- Intel Corporation
- Edward A. Burton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive frequency clock generation system
- Patent number 7,042,259
- Issue date May 9, 2006
- Intel Corporation
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Device and method for probing instantaneous high-speed local supply...
- Patent number 6,737,880
- Issue date May 18, 2004
- Intel Corporation
- Samie B. Samaan
- G01 - MEASURING TESTING
Information Patent Grant
Symmetric differential domino “AND gate”
- Patent number 6,573,755
- Issue date Jun 3, 2003
- Intel Corporation
- Thomas Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing a store operation
- Patent number 6,378,062
- Issue date Apr 23, 2002
- Intel Corporation
- Jeffery M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit to reduce charge sharing for domino circuits with pulsed cl...
- Patent number 6,377,078
- Issue date Apr 23, 2002
- Intel Corporation
- Paul D. Madland
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for blocking execution of and storing load ope...
- Patent number 5,881,262
- Issue date Mar 9, 1999
- Intel Corporation
- Jeffery M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for calculating effective memory addresses
- Patent number 5,860,154
- Issue date Jan 12, 1999
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory arrays with integrated bit line voltage stabilization circuitry
- Patent number 5,844,852
- Issue date Dec 1, 1998
- Intel Corporation
- Robert J. Murray
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for performing multiple load operations to the...
- Patent number 5,826,109
- Issue date Oct 20, 1998
- Intel Corporation
- Jeffery M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Out-of-order processor with a memory subsystem which handles specul...
- Patent number 5,751,983
- Issue date May 12, 1998
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system that maintains processor ordering consistency by sn...
- Patent number 5,748,937
- Issue date May 5, 1998
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for blocking execution of and storing load ope...
- Patent number 5,724,536
- Issue date Mar 3, 1998
- Intel Corporation
- Jeffery M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dispatching and executing a load operation...
- Patent number 5,717,882
- Issue date Feb 10, 1998
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing load operations in a computer s...
- Patent number 5,694,574
- Issue date Dec 2, 1997
- Intel Corporation
- Jeffery M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory system having data and tag arrays and multi-purpose bu...
- Patent number 5,680,572
- Issue date Oct 21, 1997
- Intel Corporation
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for caching data in a non-blocking manner usi...
- Patent number 5,671,444
- Issue date Sep 23, 1997
- Intel Corporaiton
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for executing and dispatching store operations...
- Patent number 5,664,137
- Issue date Sep 2, 1997
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for signalling a store buffer to output buffer...
- Patent number 5,606,670
- Issue date Feb 25, 1997
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for fordwarding buffered store data on an out...
- Patent number 5,588,126
- Issue date Dec 24, 1996
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for loading and storing misaligned data on an...
- Patent number 5,577,200
- Issue date Nov 19, 1996
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Source-switched charge pump circuit
- Patent number 5,532,636
- Issue date Jul 2, 1996
- Intel Corporation
- Monte F. Mar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for implementing a single clock cycle line rep...
- Patent number 5,526,510
- Issue date Jun 11, 1996
- Intel Corporation
- Haitham Akkary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for preventing incorrect fetching of an instru...
- Patent number 5,434,987
- Issue date Jul 18, 1995
- Intel Corporation
- Jeffrey M. Abramson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for generating self-timing for on-chip cache
- Patent number 5,031,141
- Issue date Jul 9, 1991
- Intel Corporation
- Douglas Guddat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing circuit for memory employing reset function
- Patent number 5,018,111
- Issue date May 21, 1991
- Intel Corporation
- Paul D. Madland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory timing circuit employing scaled-down models of bit lines usi...
- Patent number 4,926,387
- Issue date May 15, 1990
- Intel Corporation
- Paul D. Madland
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for limiting minority carrier injection in CMOS memories
- Patent number 4,727,518
- Issue date Feb 23, 1988
- Intel Corporation
- Paul D. Madland
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Adaptive frequency clock generation system
- Publication number 20050218955
- Publication date Oct 6, 2005
- Intel Corporation
- Nasser A. Kurd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and method to control self-timed and synchronous systems
- Publication number 20050146361
- Publication date Jul 7, 2005
- Edward A. Burton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Symmetric differential domino "AND gate"
- Publication number 20030001622
- Publication date Jan 2, 2003
- Thomas Fletcher
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Device and method for probing instantaneous high-speed local supply...
- Publication number 20020167327
- Publication date Nov 14, 2002
- Samie B. Samaan
- G01 - MEASURING TESTING

Paul D. Madland

Person

Patents Grantslast 30 patents

Apparatus and method to control self-timed and synchronous systems

Adaptive frequency clock generation system

Device and method for probing instantaneous high-speed local supply...

Symmetric differential domino &#x0201C;AND gate&#x0201D;

Method and apparatus for performing a store operation

Circuit to reduce charge sharing for domino circuits with pulsed cl...

Method and apparatus for blocking execution of and storing load ope...

Method and apparatus for calculating effective memory addresses

Memory arrays with integrated bit line voltage stabilization circuitry

Method and apparatus for performing multiple load operations to the...

Out-of-order processor with a memory subsystem which handles specul...

Computer system that maintains processor ordering consistency by sn...

Method and apparatus for blocking execution of and storing load ope...

Method and apparatus for dispatching and executing a load operation...

Method and apparatus for performing load operations in a computer s...

Cache memory system having data and tag arrays and multi-purpose bu...

Methods and apparatus for caching data in a non-blocking manner usi...

Method and apparatus for executing and dispatching store operations...

Method and apparatus for signalling a store buffer to output buffer...

Methods and apparatus for fordwarding buffered store data on an out...

Method and apparatus for loading and storing misaligned data on an...

Source-switched charge pump circuit

Method and apparatus for implementing a single clock cycle line rep...

Method and apparatus for preventing incorrect fetching of an instru...

Apparatus for generating self-timing for on-chip cache

Timing circuit for memory employing reset function

Memory timing circuit employing scaled-down models of bit lines usi...

Apparatus for limiting minority carrier injection in CMOS memories

Patents Applicationslast 30 patents

Adaptive frequency clock generation system

Apparatus and method to control self-timed and synchronous systems

Symmetric differential domino "AND gate"

Device and method for probing instantaneous high-speed local supply...

Symmetric differential domino “AND gate”