Paul Demone

Person

Kanata, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Deadtime adjustment for a power converter
- Patent number 11,824,438
- Issue date Nov 21, 2023
- Power Integrations, Inc.
- Robert J. Mayell
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Frequency-doubling delay locked loop
- Patent number 8,754,687
- Issue date Jun 17, 2014
- Conversant Intellectual Property Management Inc.
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power factor correction converter control offset
- Patent number 8,587,280
- Issue date Nov 19, 2013
- Power Integrations, Inc.
- Roger Colbeck
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Control arrangement for a resonant mode power converter
- Patent number 8,582,319
- Issue date Nov 12, 2013
- Power Integrations, Inc.
- Anthony Reinberger
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Frequency-doubling delay locked loop
- Patent number 8,558,593
- Issue date Oct 15, 2013
- MOSAID Technologies Incorporated
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
LLC controller with programmable fractional burst frequency
- Patent number 8,508,958
- Issue date Aug 13, 2013
- Power Integrations, Inc.
- Raymond K. Orr
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
High speed DRAM architecture with uniform access latency
- Patent number 8,503,250
- Issue date Aug 6, 2013
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Frequency-doubling delay locked loop
- Patent number 8,283,959
- Issue date Oct 9, 2012
- MOSAID Technologies Incorporated
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Control arrangement for a resonant mode power converter
- Patent number 8,274,799
- Issue date Sep 25, 2012
- Power Integrations, Inc.
- Anthony Reinberger
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Power factor correction converter control offset
- Patent number 8,248,051
- Issue date Aug 21, 2012
- Power Integrations, Inc.
- Roger Colbeck
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Power factor correction converter control offset
- Patent number 8,102,164
- Issue date Jan 24, 2012
- Power Integrations, Inc.
- Roger Colbeck
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
High speed DRAM architecture with uniform access latency
- Patent number 8,045,413
- Issue date Oct 25, 2011
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Control arrangement for a resonant mode power converter
- Patent number 8,014,172
- Issue date Sep 6, 2011
- Power Integrations, Inc.
- Anthony Reinberger
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method and apparatus for synchronization of row and column access o...
- Patent number 7,957,211
- Issue date Jun 7, 2011
- Mosaid Technologies Incorporation
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Control arrangement for a resonant mode power converter
- Patent number 7,848,117
- Issue date Dec 7, 2010
- Power Integrations, Inc.
- Anthony Reinberger
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method and apparatus for synchronization of row and column access o...
- Patent number 7,817,484
- Issue date Oct 19, 2010
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed DRAM architecture with uniform access latency
- Patent number 7,751,262
- Issue date Jul 6, 2010
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Frequency-doubling delay locked loop
- Patent number 7,746,136
- Issue date Jun 29, 2010
- MOSAID Technologies Incorporated
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for synchronization of row and column access o...
- Patent number 7,643,360
- Issue date Jan 5, 2010
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for synchronization of row and column access o...
- Patent number 7,505,336
- Issue date Mar 17, 2009
- Mosaid Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Frequency-doubling delay locked loop
- Patent number 7,456,666
- Issue date Nov 25, 2008
- Mosaid Technologies, Inc.
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed DRAM architecture with uniform access latency
- Patent number 7,450,444
- Issue date Nov 11, 2008
- Mosaid Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for synchronization of row and column access o...
- Patent number 7,277,334
- Issue date Oct 2, 2007
- Mosaid Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for simultaneous differential data sensing and...
- Patent number 7,269,075
- Issue date Sep 11, 2007
- Mosaid Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Frequency-doubling delay locked loop
- Patent number 7,116,141
- Issue date Oct 3, 2006
- Mosaid Technologies Incorporated
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for synchronization of row and column access o...
- Patent number 7,042,771
- Issue date May 9, 2006
- Mosaid Technologies Inc.
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed DRAM architecture with uniform access latency
- Patent number 7,012,850
- Issue date Mar 14, 2006
- Mosaid Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Cascaded charge pump power supply with different gate oxide thickne...
- Patent number 6,967,523
- Issue date Nov 22, 2005
- Mosaid Technologies Incorporated
- Paul W. DeMone
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed DRAM architecture with uniform access latency
- Patent number 6,891,772
- Issue date May 10, 2005
- Mosaid Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for synchronization of row and column access o...
- Patent number 6,873,568
- Issue date Mar 29, 2005
- Mosaid Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CONTROL OF A RESONANT CONVERTER USING SWITCH PATHS DURING POWER-UP
- Publication number 20230010711
- Publication date Jan 12, 2023
- Power Integrations, Inc.
- ROBERT J. MAYELL
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
DEADTIME ADJUSTMENT FOR A POWER CONVERTER
- Publication number 20220123647
- Publication date Apr 21, 2022
- POWER INTEGRATIOONS, INC.
- Robert J. Mayell
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Frequency-Doubling Delay Locked Loop
- Publication number 20140009196
- Publication date Jan 9, 2014
- MOSAID TECHNOLOGIES INCORPORATED
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LLC CONTROLLER WITH PROGRAMMABLE FRACTIONAL BURST FREQUENCY
- Publication number 20130301305
- Publication date Nov 14, 2013
- Raymond K. Orr
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
FREQUENCY-DOUBLING DELAY LOCKED LOOP
- Publication number 20130015898
- Publication date Jan 17, 2013
- MOSAID TECHNOLOGIES INCORPORATED
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER
- Publication number 20120314457
- Publication date Dec 13, 2012
- Power Integrations, Inc.
- Anthony Reinberger
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
POWER FACTOR CORRECTION CONVERTER CONTROL OFFSET
- Publication number 20120274298
- Publication date Nov 1, 2012
- Power Integrations, Inc.
- Roger Colbeck
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
LLC CONTROLLER WITH PROGRAMMABLE FRACTIONAL BURST FREQUENCY
- Publication number 20120250360
- Publication date Oct 4, 2012
- Power Integrations, Inc.
- Raymond K. Orr
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
POWER FACTOR CORRECTION CONVERTER CONTROL OFFSET
- Publication number 20120091982
- Publication date Apr 19, 2012
- Power Integrations, Inc.
- Roger Colbeck
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER
- Publication number 20120057372
- Publication date Mar 8, 2012
- Power Integrations, Inc.
- Anthony Reinberger
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
- Publication number 20120008426
- Publication date Jan 12, 2012
- MOSAID TECHNOLOGIES INCORPORATED
- Paul DEMONE
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER
- Publication number 20110044074
- Publication date Feb 24, 2011
- Power Integrations, Inc.
- Anthony Reinberger
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...
- Publication number 20100329051
- Publication date Dec 30, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Paul DEMONE
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
- Publication number 20100232237
- Publication date Sep 16, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
Frequency-Doubling Delay Locked Loop
- Publication number 20100225370
- Publication date Sep 9, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...
- Publication number 20100135089
- Publication date Jun 3, 2010
- MOSAID TECHNOLOGIES INCORPORATED
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
POWER FACTOR CORRECTION CONVERTER CONTROL OFFSET
- Publication number 20090316454
- Publication date Dec 24, 2009
- Power Integrations, Inc.
- Roger Colbeck
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...
- Publication number 20090262592
- Publication date Oct 22, 2009
- MOSAID TECHNOLOGIES INCORPORATED
- Paul DEMONE
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...
- Publication number 20090135664
- Publication date May 28, 2009
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
Frequency-doubling delay locked loop
- Publication number 20090039931
- Publication date Feb 12, 2009
- MOSAID Technologies, Inc.
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY
- Publication number 20090034347
- Publication date Feb 5, 2009
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER
- Publication number 20080198638
- Publication date Aug 21, 2008
- Anthony Reinberger
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...
- Publication number 20070286000
- Publication date Dec 13, 2007
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
Frequency-doubling delay locked loop
- Publication number 20060261866
- Publication date Nov 23, 2006
- Paul W. Demone
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High speed DRAM architecture with uniform access latency
- Publication number 20060146641
- Publication date Jul 6, 2006
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for synchronization of row and column access o...
- Publication number 20060083083
- Publication date Apr 20, 2006
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
High speed DRAM architecture with uniform access latency
- Publication number 20050180246
- Publication date Aug 18, 2005
- MOSAID Technologies Incorporated
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for synchronization of row and column access o...
- Publication number 20050036386
- Publication date Feb 17, 2005
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for accelerating signal equalization between a...
- Publication number 20040264272
- Publication date Dec 30, 2004
- Paul Demone
- G11 - INFORMATION STORAGE
Information Patent Application
High speed DRAM architecture with uniform access latency
- Publication number 20040202036
- Publication date Oct 14, 2004
- Paul Demone
- G11 - INFORMATION STORAGE

Paul Demone

Person

Patents Grantslast 30 patents

Deadtime adjustment for a power converter

Frequency-doubling delay locked loop

Power factor correction converter control offset

Control arrangement for a resonant mode power converter

Frequency-doubling delay locked loop

LLC controller with programmable fractional burst frequency

High speed DRAM architecture with uniform access latency

Frequency-doubling delay locked loop

Control arrangement for a resonant mode power converter

Power factor correction converter control offset

Power factor correction converter control offset

High speed DRAM architecture with uniform access latency

Control arrangement for a resonant mode power converter

Method and apparatus for synchronization of row and column access o...

Control arrangement for a resonant mode power converter

Method and apparatus for synchronization of row and column access o...

High speed DRAM architecture with uniform access latency

Frequency-doubling delay locked loop

Method and apparatus for synchronization of row and column access o...

Method and apparatus for synchronization of row and column access o...

Frequency-doubling delay locked loop

High speed DRAM architecture with uniform access latency

Method and apparatus for synchronization of row and column access o...

Method and apparatus for simultaneous differential data sensing and...

Frequency-doubling delay locked loop

Method and apparatus for synchronization of row and column access o...

High speed DRAM architecture with uniform access latency

Cascaded charge pump power supply with different gate oxide thickne...

High speed DRAM architecture with uniform access latency

Method and apparatus for synchronization of row and column access o...

Patents Applicationslast 30 patents

CONTROL OF A RESONANT CONVERTER USING SWITCH PATHS DURING POWER-UP

DEADTIME ADJUSTMENT FOR A POWER CONVERTER

Frequency-Doubling Delay Locked Loop

LLC CONTROLLER WITH PROGRAMMABLE FRACTIONAL BURST FREQUENCY

FREQUENCY-DOUBLING DELAY LOCKED LOOP

CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER

POWER FACTOR CORRECTION CONVERTER CONTROL OFFSET

LLC CONTROLLER WITH PROGRAMMABLE FRACTIONAL BURST FREQUENCY

POWER FACTOR CORRECTION CONVERTER CONTROL OFFSET

CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER

HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY

CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER

METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...

HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY

Frequency-Doubling Delay Locked Loop

METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...

POWER FACTOR CORRECTION CONVERTER CONTROL OFFSET

METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...

METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...

Frequency-doubling delay locked loop

HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY

CONTROL ARRANGEMENT FOR A RESONANT MODE POWER CONVERTER

METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS O...

Frequency-doubling delay locked loop

High speed DRAM architecture with uniform access latency

Method and apparatus for synchronization of row and column access o...

High speed DRAM architecture with uniform access latency

Method and apparatus for synchronization of row and column access o...

Method and apparatus for accelerating signal equalization between a...

High speed DRAM architecture with uniform access latency