Paul E. Kitchin

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compressing translation lookaside buffer (TLB) tags using a TLB met...
- Patent number 12,367,157
- Issue date Jul 22, 2025
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Filtering remote data synchronization barrier (DSB) instruction exe...
- Patent number 12,135,652
- Issue date Nov 5, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compressing translation lookaside buffer (TLB) tags using a TLB met...
- Patent number 12,130,751
- Issue date Oct 29, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency management in synchronization events
- Patent number 11,914,524
- Issue date Feb 27, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory load to load fusing
- Patent number 10,956,155
- Issue date Mar 23, 2021
- Samsung Electronics Co., Ltd.
- Paul E. Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register renaming of a shareable instruction operand cache
- Patent number 10,891,135
- Issue date Jan 12, 2021
- Samsung Electronics Co., Ltd.
- Paul E. Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to avoid cache access conflict between load and fill
- Patent number 10,649,900
- Issue date May 12, 2020
- Samsung Electronics Co., Ltd.
- Tarun Nakra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory load to load fusing
- Patent number 10,372,452
- Issue date Aug 6, 2019
- Samsung Electronics Co., Ltd.
- Paul E. Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction prefetcher dynamically controlled by readily available...
- Patent number 10,296,463
- Issue date May 21, 2019
- Samsung Electronics Co., Ltd.
- Paul E. Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory load and arithmetic load unit (ALU) fusing
- Patent number 10,275,217
- Issue date Apr 30, 2019
- Samsung Electronics Co., Ltd.
- Rama S. Gopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus related to processor sleep states
- Patent number 9,383,801
- Issue date Jul 5, 2016
- Advanced Micro Devices, Inc.
- Alexander J. Branover
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerated cache rinse when preparing a power state transition
- Patent number 9,317,100
- Issue date Apr 19, 2016
- Advanced Micro Devices, Inc.
- Paul E. Kitchin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Read-after-write hazard predictor employing confidence and sampling
- Patent number 9,286,073
- Issue date Mar 15, 2016
- Samsung Electronics Co., Ltd.
- Gerald Zuraski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling processor read-after-write hazard...
- Patent number 9,274,970
- Issue date Mar 1, 2016
- Samsung Electronics Co., Ltd.
- Paul E. Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reintialization of a processing system from volatile memory upon re...
- Patent number 9,182,999
- Issue date Nov 10, 2015
- Advanced Micro Devices, Inc.
- Andrew William Lueck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management of multiple compute units sharing a cache
- Patent number 9,043,628
- Issue date May 26, 2015
- Advanced Micro Devices, Inc.
- Paul Kitchin
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-...
- Publication number 20240427599
- Publication date Dec 26, 2024
- QUALCOMM Incorporated
- Akilesh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXPLICIT LOCKSTEP FOR FUNCTIONAL SAFETY
- Publication number 20240419451
- Publication date Dec 19, 2024
- QUALCOMM Incorporated
- Henry STRACOVSKY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FILTERING REMOTE DATA SYNCHRONIZATION BARRIER (DSB) INSTRUCTION EXE...
- Publication number 20240320157
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FILTERING REMOTE DATA SYNCHRONIZATION BARRIER (DSB) INSTRUCTION EXE...
- Publication number 20240320160
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...
- Publication number 20240273034
- Publication date Aug 15, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...
- Publication number 20240273036
- Publication date Aug 15, 2024
- QUALCOMM Incorporated
- Adrian Montero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Latency Management in Synchronization Events
- Publication number 20230281133
- Publication date Sep 7, 2023
- NUVIA, INC.
- Adrian MONTERO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES
- Publication number 20230064603
- Publication date Mar 2, 2023
- NUVIA, INC.
- Conrado BLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER RENAMING OF A SHAREABLE INSTRUCTION OPERAND CACHE
- Publication number 20200225954
- Publication date Jul 16, 2020
- Samsung Electronics Co., Ltd.
- Paul E. KITCHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LOAD TO LOAD FUSING
- Publication number 20190278603
- Publication date Sep 12, 2019
- Samsung Electronics Co., Ltd.
- Paul E. KITCHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO AVOID CACHE ACCESS CONFLICT BETWEEN LOAD AND FILL
- Publication number 20190138450
- Publication date May 9, 2019
- Samsung Electronics Co., Ltd.
- Tarun NAKRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LOAD AND ARITHMETIC LOAD UNIT (ALU) FUSING
- Publication number 20180267775
- Publication date Sep 20, 2018
- Samsung Electronics Co., Ltd.
- Rama S. GOPAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY LOAD TO LOAD FUSING
- Publication number 20180267800
- Publication date Sep 20, 2018
- Samsung Electronics Co., Ltd.
- Paul E. KITCHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE...
- Publication number 20170199739
- Publication date Jul 13, 2017
- Paul E. KITCHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOUPLING L2 BTB FROM L2 CACHE TO ACCELERATE SEARCH FOR MISS AFTER...
- Publication number 20150268961
- Publication date Sep 24, 2015
- Samsung Electronics Co., Ltd.
- Gerald D. ZURASKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ-AFTER-WRITE HAZARD PREDICTOR EMPLOYING CONFIDENCE AND SAMPLING
- Publication number 20150193334
- Publication date Jul 9, 2015
- Gerald ZURASKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR HANDLING PROCESSOR READ-AFTER-WRITE HAZARD...
- Publication number 20150186285
- Publication date Jul 2, 2015
- Samsung Electronics Co., Ltd.
- Paul E. KITCHIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATED CACHE RINSE WHEN PREPARING A POWER STATE TRANSITION
- Publication number 20140195832
- Publication date Jul 10, 2014
- Advanced Micro Devices, Inc.
- Paul E. Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC TIME COUNTER SYNCHRONIZATION
- Publication number 20140189265
- Publication date Jul 3, 2014
- Advanced Micro Devices, Inc.
- Paul Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS RELATED TO PROCESSOR SLEEP STATES
- Publication number 20140181557
- Publication date Jun 26, 2014
- Advanced Micro Devices, Inc.
- Alexander J. Branover
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SAVING PROCESSOR ARCHITECTURAL STATE IN CA...
- Publication number 20140108734
- Publication date Apr 17, 2014
- Paul Edward Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT OF MULTIPLE COMPUTE UNITS SHARING A CACHE
- Publication number 20140059371
- Publication date Feb 27, 2014
- Paul Kitchin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REINTIALIZATION OF A PROCESSING SYSTEM FROM VOLATILE MEMORY UPON RE...
- Publication number 20130326206
- Publication date Dec 5, 2013
- Advanced Micro Devices, Inc.
- Andrew William Lueck
- G06 - COMPUTING CALCULATING COUNTING

Paul E. Kitchin

Person

Patents Grantslast 30 patents

Compressing translation lookaside buffer (TLB) tags using a TLB met...

Filtering remote data synchronization barrier (DSB) instruction exe...

Compressing translation lookaside buffer (TLB) tags using a TLB met...

Latency management in synchronization events

Memory load to load fusing

Register renaming of a shareable instruction operand cache

Method to avoid cache access conflict between load and fill

Memory load to load fusing

Instruction prefetcher dynamically controlled by readily available...

Memory load and arithmetic load unit (ALU) fusing

Methods and apparatus related to processor sleep states

Accelerated cache rinse when preparing a power state transition

Read-after-write hazard predictor employing confidence and sampling

Method and apparatus for handling processor read-after-write hazard...

Reintialization of a processing system from volatile memory upon re...

Power management of multiple compute units sharing a cache

Patents Applicationslast 30 patents

PROVIDING PHYSICAL REGISTER (PR) SWAP MEMORY RENAMING IN PROCESSOR-...

EXPLICIT LOCKSTEP FOR FUNCTIONAL SAFETY

FILTERING REMOTE DATA SYNCHRONIZATION BARRIER (DSB) INSTRUCTION EXE...

FILTERING REMOTE DATA SYNCHRONIZATION BARRIER (DSB) INSTRUCTION EXE...

COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...

COMPRESSING TRANSLATION LOOKASIDE BUFFER (TLB) TAGS USING A TLB MET...

Latency Management in Synchronization Events

SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES

REGISTER RENAMING OF A SHAREABLE INSTRUCTION OPERAND CACHE

MEMORY LOAD TO LOAD FUSING

METHOD TO AVOID CACHE ACCESS CONFLICT BETWEEN LOAD AND FILL

MEMORY LOAD AND ARITHMETIC LOAD UNIT (ALU) FUSING

MEMORY LOAD TO LOAD FUSING

INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE...

DECOUPLING L2 BTB FROM L2 CACHE TO ACCELERATE SEARCH FOR MISS AFTER...

READ-AFTER-WRITE HAZARD PREDICTOR EMPLOYING CONFIDENCE AND SAMPLING

METHOD AND APPARATUS FOR HANDLING PROCESSOR READ-AFTER-WRITE HAZARD...

ACCELERATED CACHE RINSE WHEN PREPARING A POWER STATE TRANSITION

ATOMIC TIME COUNTER SYNCHRONIZATION

METHODS AND APPARATUS RELATED TO PROCESSOR SLEEP STATES

METHOD AND APPARATUS FOR SAVING PROCESSOR ARCHITECTURAL STATE IN CA...

POWER MANAGEMENT OF MULTIPLE COMPUTE UNITS SHARING A CACHE

REINTIALIZATION OF A PROCESSING SYSTEM FROM VOLATILE MEMORY UPON RE...