Paul Edward HANHAM

Person

Didcot, GB

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for buffer allocation management for a memory device
- Patent number 12,118,235
- Issue date Oct 15, 2024
- Kioxia Corporation
- Paul Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method for high performance memory debug record generati...
- Patent number 11,847,037
- Issue date Dec 19, 2023
- Kioxia Corporation
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient decoding of n-dimensional error correction codes
- Patent number 11,394,402
- Issue date Jul 19, 2022
- Kioxia Corporation
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient decoding of n-dimensional error correction codes
- Patent number 10,886,947
- Issue date Jan 5, 2021
- TOSHIBA MEMORY CORPORATION
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non volatile memory controller device and method for adjustment
- Patent number 10,872,013
- Issue date Dec 22, 2020
- TOSHIBA MEMORY CORPORATION
- David Symons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pooled frontline ECC decoders in memory systems
- Patent number 10,747,613
- Issue date Aug 18, 2020
- TOSHIBA MEMORY CORPORATION
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for improved memory error rate estimation
- Patent number 10,613,927
- Issue date Apr 7, 2020
- TOSHIBA MEMORY CORPORATION
- David Malcolm Symons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power error correcting code (ECC) system
- Patent number 10,498,362
- Issue date Dec 3, 2019
- Kabushiki Kaisha Toshiba
- Paul Hanham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimal LDPC bit flip decision
- Patent number 10,447,301
- Issue date Oct 15, 2019
- TOSHIBA MEMORY CORPORATION
- Paul Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low BER hard-decision LDPC decoder
- Patent number 10,404,279
- Issue date Sep 3, 2019
- TOSHIBA MEMORY CORPORATION
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft decision LDPC decoder with improved LLR from neighboring bits
- Patent number 10,340,951
- Issue date Jul 2, 2019
- TOSHIBA MEMORY CORPORATION
- David Symons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low BER hard-decision LDPC decoder
- Patent number 10,084,479
- Issue date Sep 25, 2018
- TOSHIBA MEMORY CORPORATION
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory controller with error correction (ECC) tuning v...
- Patent number 9,407,294
- Issue date Aug 2, 2016
- Kabushi Kaisha Toshiba
- Paul Edward Hanham
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR BUFFER ALLOCATION MANAGEMENT FOR A MEMORY DEVICE
- Publication number 20230047029
- Publication date Feb 16, 2023
- KIOXIA Corporation
- Paul Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE AND METHOD FOR HIGH PERFORMANCE MEMORY DEBUG RECORD GENERATI...
- Publication number 20220083442
- Publication date Mar 17, 2022
- Toshiba Memory Corporation
- Paul Edward HANHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DECODING OF N-DIMENSIONAL ERROR CORRECTION CODES
- Publication number 20210126653
- Publication date Apr 29, 2021
- Toshiba Memory Corporation
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON VOLATILE MEMORY CONTROLLER DEVICE AND METHOD FOR ADJUSTMENT
- Publication number 20200293398
- Publication date Sep 17, 2020
- Toshiba Memory Corporation
- David Symons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DECODING OF N-DIMENSIONAL ERROR CORRECTION CODES
- Publication number 20200201708
- Publication date Jun 25, 2020
- Toshiba Memory Corporation
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POOLED FRONTLINE ECC DECODERS IN MEMORY SYSTEMS
- Publication number 20200081773
- Publication date Mar 12, 2020
- Toshiba Memory Corporation
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW BER HARD-DECISION LDPC DECODER
- Publication number 20190103882
- Publication date Apr 4, 2019
- Toshiba Memory Corporation
- Paul Edward Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimal LDPC Bit Flip Decision
- Publication number 20190081639
- Publication date Mar 14, 2019
- Toshiba Memory Corporation
- Paul Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Soft Decision LDPC Decoder With Improved LLR From Neighboring Bits
- Publication number 20190081641
- Publication date Mar 14, 2019
- Toshiba Memory Corporation
- David Symons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER ERROR CORRECTING CODE (ECC) SYSTEM
- Publication number 20180175882
- Publication date Jun 21, 2018
- Kabushiki Kaisha Toshiba
- Paul Hanham
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hybrid LDPC-SEC/SECDED Decoding
- Publication number 20180175885
- Publication date Jun 21, 2018
- Toshiba Memory Corporation
- Paul Hanham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY CONTROLLER WITH ERROR CORRECTION (ECC) TUNING...
- Publication number 20160006462
- Publication date Jan 7, 2016
- OCZ STORAGE SOLUTIONS, INC.
- Paul Edward HANHAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW BER HARD-DECISION LDPC DECODER
- Publication number 20160006459
- Publication date Jan 7, 2016
- OCZ STORAGE SOLUTIONS, INC.
- Paul Edward HANHAM
- G06 - COMPUTING CALCULATING COUNTING

Paul Edward HANHAM

Person

Patents Grantslast 30 patents

Method and system for buffer allocation management for a memory device

Device and method for high performance memory debug record generati...

Efficient decoding of n-dimensional error correction codes

Efficient decoding of n-dimensional error correction codes

Non volatile memory controller device and method for adjustment

Pooled frontline ECC decoders in memory systems

System and method for improved memory error rate estimation

Low power error correcting code (ECC) system

Optimal LDPC bit flip decision

Low BER hard-decision LDPC decoder

Soft decision LDPC decoder with improved LLR from neighboring bits

Low BER hard-decision LDPC decoder

Non-volatile memory controller with error correction (ECC) tuning v...

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR BUFFER ALLOCATION MANAGEMENT FOR A MEMORY DEVICE

DEVICE AND METHOD FOR HIGH PERFORMANCE MEMORY DEBUG RECORD GENERATI...

EFFICIENT DECODING OF N-DIMENSIONAL ERROR CORRECTION CODES

NON VOLATILE MEMORY CONTROLLER DEVICE AND METHOD FOR ADJUSTMENT

EFFICIENT DECODING OF N-DIMENSIONAL ERROR CORRECTION CODES

POOLED FRONTLINE ECC DECODERS IN MEMORY SYSTEMS

LOW BER HARD-DECISION LDPC DECODER

Optimal LDPC Bit Flip Decision

Soft Decision LDPC Decoder With Improved LLR From Neighboring Bits

LOW POWER ERROR CORRECTING CODE (ECC) SYSTEM

Hybrid LDPC-SEC/SECDED Decoding

NON-VOLATILE MEMORY CONTROLLER WITH ERROR CORRECTION (ECC) TUNING...

LOW BER HARD-DECISION LDPC DECODER