Paul G. Filseth

Person

Los Gatos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Correcting errors in miscorrected codewords using list decoding
- Patent number 8,898,539
- Issue date Nov 25, 2014
- LSI Corporation
- Yang Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Alternate galois field advanced encryption standard round
- Patent number 8,411,853
- Issue date Apr 2, 2013
- LSI Corporation
- Paul G. Filseth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High performance arithmetic logic unit (ALU) for cryptographic appl...
- Patent number 8,359,479
- Issue date Jan 22, 2013
- LSI Corporation
- Mikhail I. Grinchuk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multimode block cipher architectures
- Patent number 8,023,644
- Issue date Sep 20, 2011
- LSI Corporation
- Anatoli A. Bolotov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for reducing inter-layer capacitance in integrate...
- Patent number 8,015,540
- Issue date Sep 6, 2011
- LSI Corporation
- Kunal N. Taravade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flexible hardware architecture for ECC/HECC based cryptography
- Patent number 7,961,872
- Issue date Jun 14, 2011
- LSI Corporation
- Anatoli A. Bolotov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for reducing inter-layer capacitance in integrate...
- Patent number 7,396,760
- Issue date Jul 8, 2008
- LSI Corporation
- Kunal N. Taravade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
OPC based illumination optimization with mask error constraints
- Patent number 7,264,906
- Issue date Sep 4, 2007
- LSI Corporation
- Ebo H. Croffie
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Adaptive Sem edge recognition algorithm
- Patent number 7,171,047
- Issue date Jan 30, 2007
- LSI Logic Corporation
- Mikhail Grinchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mask defect analysis for both horizontal and vertical processing ef...
- Patent number 7,149,340
- Issue date Dec 12, 2006
- LSI Logic Corporation
- Paul Filseth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mask correction for photolithographic processes
- Patent number 6,934,410
- Issue date Aug 23, 2005
- LSI Logic Corporation
- Stanislav V. Aleshin
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Automatic calibration of a masking process simulator
- Patent number 6,868,355
- Issue date Mar 15, 2005
- LSI Logic Corporation
- Lav Ivanovic
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Wafer process critical dimension, alignment, and registration analy...
- Patent number 6,782,525
- Issue date Aug 24, 2004
- LSI Logic Corporation
- Mario Garza
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Automatic calibration of a masking process simulator
- Patent number 6,768,958
- Issue date Jul 27, 2004
- LSI Logic Corporation
- Lav Ivanovic
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Optical and etch proximity correction
- Patent number 6,701,511
- Issue date Mar 2, 2004
- LSI Logic Corporation
- Paul G. Filseth
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Mask correction optimization
- Patent number 6,611,953
- Issue date Aug 26, 2003
- LSI Logic Corporation
- Paul G. Filseth
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for flattening hierarchical design descriptions
- Patent number 5,473,546
- Issue date Dec 5, 1995
- LSI Logic Corporation
- Paul Filseth
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING
- Publication number 20140075264
- Publication date Mar 13, 2014
- LSI Corporation
- Yang Han
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTIPLE-MODE CRYPTOGRAPHIC MODULE USABLE WITH MEMORY CONTROLLERS
- Publication number 20110255689
- Publication date Oct 20, 2011
- LSI Corporation
- Anatoli Bolotov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Alternate galois field advanced encryption standard round
- Publication number 20100057823
- Publication date Mar 4, 2010
- Paul G. Filseth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
High performance arithmetic logic unit (ALU) for cryptographic appl...
- Publication number 20100017622
- Publication date Jan 21, 2010
- Mikhail I. Grinchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for reducing inter-layer capacitance in integrate...
- Publication number 20080235643
- Publication date Sep 25, 2008
- LSI Logic Corporation
- Kunal N. Taravade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flexible hardware architecture for ECC/HECC based crytography
- Publication number 20080130873
- Publication date Jun 5, 2008
- LSI Corporation
- Anatoli A. Bolotov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTIMODE BLOCK CIPHER ARCHITECTURES
- Publication number 20080130872
- Publication date Jun 5, 2008
- LSI Corporation
- Anatoli A. Bolotov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for reducing inter-layer capacitance in integrate...
- Publication number 20060105564
- Publication date May 18, 2006
- Kunal N. Taravade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPC based illumination optimization with mask error constraints
- Publication number 20050196681
- Publication date Sep 8, 2005
- Ebo H. Croffle
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Automatic calibration of a masking process simulator
- Publication number 20040199349
- Publication date Oct 7, 2004
- Lav Ivanovic
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Adaptive SEM edge recognition algorithm
- Publication number 20040120578
- Publication date Jun 24, 2004
- Mikhail Grinchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC CALIBRATION OF A MASKING PROCESS SIMULATOR
- Publication number 20040102912
- Publication date May 27, 2004
- Lav Ivanovic
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Mask defect analysis for both horizontal and vertical processing ef...
- Publication number 20040057610
- Publication date Mar 25, 2004
- Paul Filseth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wafer process critical dimension, alignment, and registration analy...
- Publication number 20040049760
- Publication date Mar 11, 2004
- Mario Garza
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Paul G. Filseth

Person

Patents Grantslast 30 patents

Correcting errors in miscorrected codewords using list decoding

Alternate galois field advanced encryption standard round

High performance arithmetic logic unit (ALU) for cryptographic appl...

Multimode block cipher architectures

Method and system for reducing inter-layer capacitance in integrate...

Flexible hardware architecture for ECC/HECC based cryptography

Method and system for reducing inter-layer capacitance in integrate...

OPC based illumination optimization with mask error constraints

Adaptive Sem edge recognition algorithm

Mask defect analysis for both horizontal and vertical processing ef...

Mask correction for photolithographic processes

Automatic calibration of a masking process simulator

Wafer process critical dimension, alignment, and registration analy...

Automatic calibration of a masking process simulator

Optical and etch proximity correction

Mask correction optimization

Method for flattening hierarchical design descriptions

Patents Applicationslast 30 patents

CORRECTING ERRORS IN MISCORRECTED CODEWORDS USING LIST DECODING

MULTIPLE-MODE CRYPTOGRAPHIC MODULE USABLE WITH MEMORY CONTROLLERS

Alternate galois field advanced encryption standard round

High performance arithmetic logic unit (ALU) for cryptographic appl...

Method and system for reducing inter-layer capacitance in integrate...

Flexible hardware architecture for ECC/HECC based crytography

MULTIMODE BLOCK CIPHER ARCHITECTURES

Method and system for reducing inter-layer capacitance in integrate...

OPC based illumination optimization with mask error constraints

Automatic calibration of a masking process simulator

Adaptive SEM edge recognition algorithm

AUTOMATIC CALIBRATION OF A MASKING PROCESS SIMULATOR

Mask defect analysis for both horizontal and vertical processing ef...

Wafer process critical dimension, alignment, and registration analy...