Paul G. Villarrubia

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Region-based power grid generation through modification of an initi...
- Patent number 11,916,384
- Issue date Feb 27, 2024
- International Business Machines Corporation
- David Wolpert
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Automated design closure with abutted hierarchy
- Patent number 11,080,456
- Issue date Aug 3, 2021
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element graph-based placement in integrated circuit design
- Patent number 11,080,443
- Issue date Aug 3, 2021
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-cycle latch tree synthesis
- Patent number 11,074,379
- Issue date Jul 27, 2021
- International Business Machines Corporation
- Lakshmi N. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchy-driven logical and physical synthesis co-optimization
- Patent number 10,891,411
- Issue date Jan 12, 2021
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Propagating constants of structured soft blocks while preserving th...
- Patent number 10,803,224
- Issue date Oct 13, 2020
- International Business Machines Corporation
- Salim Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Model-based refinement of the placement process in integrated circu...
- Patent number 10,762,271
- Issue date Sep 1, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large cluster persistence during placement optimization of integrat...
- Patent number 10,685,160
- Issue date Jun 16, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhancing stability of half perimeter wire length (HPWL)-driven ana...
- Patent number 10,635,773
- Issue date Apr 28, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element graph-based placement in integrated circuit design
- Patent number 10,558,775
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integer arithmetic method for wire length minimization in global pl...
- Patent number 10,528,695
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Alexey Y. Lvov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large cluster persistence during placement optimization of integrat...
- Patent number 10,140,409
- Issue date Nov 27, 2018
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing adjustments across transparent latches to facilitate power r...
- Patent number 9,754,062
- Issue date Sep 5, 2017
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Element placement in circuit design based on preferred location
- Patent number 9,524,363
- Issue date Dec 20, 2016
- GLOBALFOUNDRIES Inc.
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large cluster persistence during placement optimization of integrat...
- Patent number 9,495,501
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi power synthesis in digital circuit design
- Patent number 9,483,596
- Issue date Nov 1, 2016
- International Business Machines Corporation
- John T. Badar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary latch and logic placement to satisfy timing constraints
- Patent number 9,098,669
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured placement of hierarchical soft blocks during physical sy...
- Patent number 8,954,915
- Issue date Feb 10, 2015
- International Business Machines Corporation
- Yiu-Hing Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured placement of latches/flip-flops to minimize clock power...
- Patent number 8,954,912
- Issue date Feb 10, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling for parallel processing of regionally-constrained placem...
- Patent number 8,930,867
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing centric design closure
- Patent number 8,826,215
- Issue date Sep 2, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Facilitating the design of a clock grid in an integrated circuit
- Patent number 8,799,846
- Issue date Aug 5, 2014
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-placement cell shifting
- Patent number 8,782,584
- Issue date Jul 15, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling for parallel processing of regionally-constrained placem...
- Patent number 8,578,315
- Issue date Nov 5, 2013
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning for hardware-accelerated functional verification
- Patent number 8,555,221
- Issue date Oct 8, 2013
- International Business Machines Corporation
- Michael D. Moffitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-placement cell shifting
- Patent number 8,495,534
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer-aware routing in integrated circuit design
- Patent number 8,370,782
- Issue date Feb 5, 2013
- International Business Machines Corporation
- Chuck Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detailed routability by cell placement
- Patent number 8,347,257
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partitioning for hardware-accelerated functional verification
- Patent number 8,327,304
- Issue date Dec 4, 2012
- International Business Machines Corporation
- Michael D. Moffitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduling for parallel processing of regionally-constrained placem...
- Patent number 8,245,173
- Issue date Aug 14, 2012
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BIT FLIP AWARE LATCH PLACEMENT
- Publication number 20240104282
- Publication date Mar 28, 2024
- International Business Machines Corporation
- Benjamin Neil Trombley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED ALIGNMENT FOR GLOBAL PLACEMENT IN A CIRCUIT
- Publication number 20230385503
- Publication date Nov 30, 2023
- International Business Machines Corporation
- Alexey Y LVOV
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHORT NET PIN ALIGNMENT FOR ROUTING
- Publication number 20230306179
- Publication date Sep 28, 2023
- International Business Machines Corporation
- Hua XIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER STAPLE AVOIDANCE FOR ROUTING VIA REDUCTION
- Publication number 20230237233
- Publication date Jul 27, 2023
- International Business Machines Corporation
- Hua XIANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGION-BASED POWER GRID GENERATION THROUGH MODIFICATION OF AN INITI...
- Publication number 20230090855
- Publication date Mar 23, 2023
- International Business Machines Corporation
- David Wolpert
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY
- Publication number 20210165856
- Publication date Jun 3, 2021
- International Business Machines Corporation
- Michael Kazda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-CYCLE LATCH TREE SYNTHESIS
- Publication number 20200311221
- Publication date Oct 1, 2020
- International Business Machines Corporation
- Lakshmi N. Reddy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHY-DRIVEN LOGICAL AND PHYSICAL SYNTHESIS CO-OPTIMIZATION
- Publication number 20200175122
- Publication date Jun 4, 2020
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROPAGATING CONSTANTS OF STRUCTURED SOFT BLOCKS WHILE PRESERVING TH...
- Publication number 20200159882
- Publication date May 21, 2020
- International Business Machines Corporation
- Salim Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ELEMENT GRAPH-BASED PLACEMENT IN INTEGRATED CIRCUIT DESIGN
- Publication number 20200125779
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCING STABILITY OF HALF PERIMETER WIRE LENGTH (HPWL)-DRIVEN ANA...
- Publication number 20200125690
- Publication date Apr 23, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODEL-BASED REFINEMENT OF THE PLACEMENT PROCESS IN INTEGRATED CIRCU...
- Publication number 20200104453
- Publication date Apr 2, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGER ARITHMETIC METHOD FOR WIRE LENGTH MINIMIZATION IN GLOBAL PL...
- Publication number 20200034507
- Publication date Jan 30, 2020
- International Business Machines Corporation
- Alexey Y. Lvov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ELEMENT GRAPH-BASED PLACEMENT IN INTEGRATED CIRCUIT DESIGN
- Publication number 20190188352
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...
- Publication number 20190026418
- Publication date Jan 24, 2019
- International Business Machines Corporation
- MYUNG-CHUL KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...
- Publication number 20170220722
- Publication date Aug 3, 2017
- International Business Machines Corporation
- MYUNG-CHUL KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING ADJUSTMENTS ACROSS TRANSPARENT LATCHES TO FACILITATE POWER R...
- Publication number 20170132347
- Publication date May 11, 2017
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS
- Publication number 20150199465
- Publication date Jul 16, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURED PLACEMENT OF HIERARCHICAL SOFT BLOCKS DURING PHYSICAL SY...
- Publication number 20140359546
- Publication date Dec 4, 2014
- International Business Machines Corporation
- Yiu-Hing Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...
- Publication number 20140149957
- Publication date May 29, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling for Parallel Processing of Regionally-Constrained Placem...
- Publication number 20140033154
- Publication date Jan 30, 2014
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-PLACEMENT CELL SHIFTING
- Publication number 20130346938
- Publication date Dec 26, 2013
- International Business Machines Corporation
- Charles J Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION
- Publication number 20130326455
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION
- Publication number 20120317527
- Publication date Dec 13, 2012
- International Business Machines Corporation
- MICHAEL D. MOFFITT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN
- Publication number 20120297355
- Publication date Nov 22, 2012
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling for Parallel Processing of Regionally-Constrained Placem...
- Publication number 20120284733
- Publication date Nov 8, 2012
- International Business Machines Corporation
- Gi-Joon Nam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION
- Publication number 20120131530
- Publication date May 24, 2012
- International Business Machines Corporation
- MICHAEL D. MOFFITT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN
- Publication number 20110320992
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Chuck ALPERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETAILED ROUTABILITY BY CELL PLACEMENT
- Publication number 20110302545
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-PLACEMENT CELL SHIFTING
- Publication number 20110302544
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Paul G. Villarrubia

Person

Patents Grantslast 30 patents

Region-based power grid generation through modification of an initi...

Automated design closure with abutted hierarchy

Memory element graph-based placement in integrated circuit design

Multi-cycle latch tree synthesis

Hierarchy-driven logical and physical synthesis co-optimization

Propagating constants of structured soft blocks while preserving th...

Model-based refinement of the placement process in integrated circu...

Large cluster persistence during placement optimization of integrat...

Enhancing stability of half perimeter wire length (HPWL)-driven ana...

Memory element graph-based placement in integrated circuit design

Integer arithmetic method for wire length minimization in global pl...

Large cluster persistence during placement optimization of integrat...

Timing adjustments across transparent latches to facilitate power r...

Element placement in circuit design based on preferred location

Large cluster persistence during placement optimization of integrat...

Multi power synthesis in digital circuit design

Boundary latch and logic placement to satisfy timing constraints

Structured placement of hierarchical soft blocks during physical sy...

Structured placement of latches/flip-flops to minimize clock power...

Scheduling for parallel processing of regionally-constrained placem...

Routing centric design closure

Facilitating the design of a clock grid in an integrated circuit

Post-placement cell shifting

Scheduling for parallel processing of regionally-constrained placem...

Partitioning for hardware-accelerated functional verification

Post-placement cell shifting

Buffer-aware routing in integrated circuit design

Detailed routability by cell placement

Partitioning for hardware-accelerated functional verification

Scheduling for parallel processing of regionally-constrained placem...

Patents Applicationslast 30 patents

BIT FLIP AWARE LATCH PLACEMENT

ENHANCED ALIGNMENT FOR GLOBAL PLACEMENT IN A CIRCUIT

SHORT NET PIN ALIGNMENT FOR ROUTING

POWER STAPLE AVOIDANCE FOR ROUTING VIA REDUCTION

REGION-BASED POWER GRID GENERATION THROUGH MODIFICATION OF AN INITI...

AUTOMATED DESIGN CLOSURE WITH ABUTTED HIERARCHY

MULTI-CYCLE LATCH TREE SYNTHESIS

HIERARCHY-DRIVEN LOGICAL AND PHYSICAL SYNTHESIS CO-OPTIMIZATION

PROPAGATING CONSTANTS OF STRUCTURED SOFT BLOCKS WHILE PRESERVING TH...

MEMORY ELEMENT GRAPH-BASED PLACEMENT IN INTEGRATED CIRCUIT DESIGN

ENHANCING STABILITY OF HALF PERIMETER WIRE LENGTH (HPWL)-DRIVEN ANA...

MODEL-BASED REFINEMENT OF THE PLACEMENT PROCESS IN INTEGRATED CIRCU...

INTEGER ARITHMETIC METHOD FOR WIRE LENGTH MINIMIZATION IN GLOBAL PL...

MEMORY ELEMENT GRAPH-BASED PLACEMENT IN INTEGRATED CIRCUIT DESIGN

LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...

LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...

TIMING ADJUSTMENTS ACROSS TRANSPARENT LATCHES TO FACILITATE POWER R...

BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS

STRUCTURED PLACEMENT OF HIERARCHICAL SOFT BLOCKS DURING PHYSICAL SY...

STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...

Scheduling for Parallel Processing of Regionally-Constrained Placem...

POST-PLACEMENT CELL SHIFTING

ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION

PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION

WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN

Scheduling for Parallel Processing of Regionally-Constrained Placem...

PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION

BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN

DETAILED ROUTABILITY BY CELL PLACEMENT

POST-PLACEMENT CELL SHIFTING