Paul H. L. M. Schram

Person

Bergen op zoom, NL

People

Patents Grantslast 30 patents

Information Patent Grant
Hardware delay compensation in digital phase locked loop
- Patent number 9,667,237
- Issue date May 30, 2017
- Microsemi Semiconductor ULC
- Qu Gary Jin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for generating clock signals having a PLL part and synthe...
- Patent number 9,647,674
- Issue date May 9, 2017
- Microsemi Semiconductor ULC
- Paul H. L. M. Schram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase locked loop with jump-free holdover mode
- Patent number 9,634,675
- Issue date Apr 25, 2017
- Microsemi Semiconductor ULC
- Paul H. L. M. Schram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase locked loop arrangement with master clock redundancy
- Patent number 9,595,972
- Issue date Mar 14, 2017
- Microsemi Semiconductor ULC
- Slobodan Milijevic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase locked loop with accurate alignment among output clocks
- Patent number 9,584,138
- Issue date Feb 28, 2017
- Microsemi Semiconductor ULC
- Krste Mitric
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL glitchless phase adjustment system
- Patent number 9,124,415
- Issue date Sep 1, 2015
- Microsemi Semiconductor ULC
- David Colby
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase locked loop with the ability to accurately apply phase offset...
- Patent number 9,094,185
- Issue date Jul 28, 2015
- Microsemi Semiconductor ULC
- Paul H. L. M. Schram
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase locked loop with simultaneous locking to low and high frequen...
- Patent number 8,907,706
- Issue date Dec 9, 2014
- Microsemi Semiconductor ULC
- Krste Mitric
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Phase Locked Loop with Accurate Alignment among Output Clocks
- Publication number 20160301417
- Publication date Oct 13, 2016
- MICROSEMI SEMICONDUCTOR ULC
- Krste Mitric
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Digital Phase Locked Loop Arrangement with Master Clock Redundancy
- Publication number 20160301416
- Publication date Oct 13, 2016
- MICROSEMI SEMICONDUCTOR ULC
- Slobodan Milijevic
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus for Generating Clock Signals having a PLL part and Synthe...
- Publication number 20160301419
- Publication date Oct 13, 2016
- MICROSEMI SEMICONDUCTOR ULC
- Paul H.L.M. Schram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hardware Delay Compensation in Digital Phase Locked Loop
- Publication number 20160294401
- Publication date Oct 6, 2016
- MICROSEMI SEMICONDUCTOR ULC
- Qu Gary Jin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase Locked Loop with Jump-Free Holdover Mode
- Publication number 20160294399
- Publication date Oct 6, 2016
- MICROSEMI SEMICONDUCTOR ULC
- Paul H.L.M. Schram
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase Locked Loop with the Ability to Accurately Apply Phase Offset...
- Publication number 20150207619
- Publication date Jul 23, 2015
- MICROSEMI SEMICONDUCTOR ULC
- Paul H.L.M. SCHRAM
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PLL GLITCHLESS PHASE ADJUSTMENT SYSTEM
- Publication number 20150207620
- Publication date Jul 23, 2015
- MICROSEMI SEMICONDUCTOR ULC
- David COLBY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUEN...
- Publication number 20140320181
- Publication date Oct 30, 2014
- MICROSEMI SEMICONDUCTOR ULC
- Krste Mitric
- H03 - BASIC ELECTRONIC CIRCUITRY

Paul H. L. M. Schram

Person

Patents Grantslast 30 patents

Hardware delay compensation in digital phase locked loop

Apparatus for generating clock signals having a PLL part and synthe...

Phase locked loop with jump-free holdover mode

Digital phase locked loop arrangement with master clock redundancy

Phase locked loop with accurate alignment among output clocks

PLL glitchless phase adjustment system

Phase locked loop with the ability to accurately apply phase offset...

Phase locked loop with simultaneous locking to low and high frequen...

Patents Applicationslast 30 patents

Phase Locked Loop with Accurate Alignment among Output Clocks

Digital Phase Locked Loop Arrangement with Master Clock Redundancy

Apparatus for Generating Clock Signals having a PLL part and Synthe...

Hardware Delay Compensation in Digital Phase Locked Loop

Phase Locked Loop with Jump-Free Holdover Mode

Phase Locked Loop with the Ability to Accurately Apply Phase Offset...

PLL GLITCHLESS PHASE ADJUSTMENT SYSTEM

PHASE LOCKED LOOP WITH SIMULTANEOUS LOCKING TO LOW AND HIGH FREQUEN...