Paul J. Dickinson

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Post-silicon repair of on-die networks
- Patent number 9,178,750
- Issue date Nov 3, 2015
- Oracle International Corporation
- Robert P Masleid
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Testing multi-core processors
- Patent number 8,214,703
- Issue date Jul 3, 2012
- Oracle America, Inc.
- Murali Mohan Reddy Gala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for determining circuit interdependencies
- Patent number 8,099,705
- Issue date Jan 17, 2012
- Oracle America, Inc.
- Paul J. Dickinson
- G01 - MEASURING TESTING
Information Patent Grant
At-speed scan testing of memory arrays
- Patent number 8,065,572
- Issue date Nov 22, 2011
- Oracle America, Inc.
- Thomas A. Ziaja
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing memory array at operational speed using scan
- Patent number 7,779,316
- Issue date Aug 17, 2010
- Oracle America, Inc.
- Ishwardutt Parulkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheme for screening weak memory cell
- Patent number 7,679,978
- Issue date Mar 16, 2010
- Sun Microsystems, Inc.
- Hua-Yu Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of displaying an image of device test data
- Patent number 7,009,625
- Issue date Mar 7, 2006
- Sun Microsystems, Inc.
- Paul J. Dickinson
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Spatial and temporal alignment of a scan dump for debug of scan-bas...
- Patent number 6,507,925
- Issue date Jan 14, 2003
- Sun Microsystems, Inc.
- Sridhar Narayanan
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
POST-SILICON REPAIR OF ON-DIE NETWORKS
- Publication number 20140140205
- Publication date May 22, 2014
- Oracle International Corporation
- Robert P. Masleid
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AT-SPEED SCAN TESTING OF MEMORY ARRAYS
- Publication number 20100332924
- Publication date Dec 30, 2010
- Thomas A. Ziaja
- G01 - MEASURING TESTING
Information Patent Application
TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES
- Publication number 20100281442
- Publication date Nov 4, 2010
- SUN MICROSYSTEMS, INC.
- Paul J. Dickinson
- G01 - MEASURING TESTING
Information Patent Application
TESTING MULTI-CORE PROCESSORS
- Publication number 20100235683
- Publication date Sep 16, 2010
- SUN MICROSYSTEMS, INC.
- Murali Mohan Reddy Gala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF TESTING MEMORY ARRAY AT OPERATIONAL SPEED USING SCAN
- Publication number 20090150729
- Publication date Jun 11, 2009
- SUN MICROSYSTEMS, INC.
- Ishwardutt Parulkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of displaying device test data
- Publication number 20040179021
- Publication date Sep 16, 2004
- Paul J. Dickinson
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
Method of displaying an image of device test data
- Publication number 20040179024
- Publication date Sep 16, 2004
- Paul J. Dickinson
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS

Paul J. Dickinson

Person

Patents Grantslast 30 patents

Post-silicon repair of on-die networks

Testing multi-core processors

Technique for determining circuit interdependencies

At-speed scan testing of memory arrays

Method of testing memory array at operational speed using scan

Scheme for screening weak memory cell

Method of displaying an image of device test data

Spatial and temporal alignment of a scan dump for debug of scan-bas...

Patents Applicationslast 30 patents

POST-SILICON REPAIR OF ON-DIE NETWORKS

AT-SPEED SCAN TESTING OF MEMORY ARRAYS

TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES

TESTING MULTI-CORE PROCESSORS

METHOD OF TESTING MEMORY ARRAY AT OPERATIONAL SPEED USING SCAN

Method of displaying device test data

Method of displaying an image of device test data