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Paul Joseph Murtagh
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Duluth, GA, US
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Patents Grants
last 30 patents
Information
Patent Grant
DRAM interface circuits that support fast deskew calibration and me...
Patent number
7,555,668
Issue date
Jun 30, 2009
Integrated Device Technology, Inc.
Paul Joseph Murtagh
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
DRAM interface circuits having enhanced skew, slew rate and impedan...
Patent number
7,079,446
Issue date
Jul 18, 2006
Integrated Device Technology, Inc.
Paul Murtagh
G11 - INFORMATION STORAGE
Information
Patent Grant
Dynamic phase-locked loop circuits and methods of operation thereof
Patent number
7,046,093
Issue date
May 16, 2006
Intergrated Device Technology, Inc.
Declan McDonagh
Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information
Patent Grant
Delay-locked loop (DLL) integrated circuits having high bandwidth a...
Patent number
6,867,627
Issue date
Mar 15, 2005
Integrated Device Technology, Inc.
Paul Murtagh
H03 - BASIC ELECTRONIC CIRCUITRY
Patents Applications
last 30 patents
Information
Patent Application
DRAM interface circuits that support fast deskew calibration and me...
Publication number
20080022145
Publication date
Jan 24, 2008
Paul Joseph Murtagh
G06 - COMPUTING CALCULATING COUNTING