Paul L. Garbarino

Person

Ridgefield, CT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Testing method and structure for leakage current characterization i...
- Patent number 4,542,340
- Issue date Sep 17, 1985
- IBM Corporation
- Satya N. Chakravarti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with improved isolation between two layers...
- Patent number 4,498,095
- Issue date Feb 5, 1985
- International Business Machines Corporation
- Paul L. Garbarino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Borderless diffusion contact process and structure
- Patent number 4,409,722
- Issue date Oct 18, 1983
- International Business Machines Corporation
- Robert C. Dockerty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making dense vertical FET's
- Patent number 4,407,058
- Issue date Oct 4, 1983
- International Business Machines Corporation
- Joseph J. Fatula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FET Memory cell structure and process
- Patent number 4,397,075
- Issue date Aug 9, 1983
- International Business Machines Corporation
- Joseph J. Fatula
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making an electrical contact to a silicon substrate thro...
- Patent number 4,341,009
- Issue date Jul 27, 1982
- International Business Machines Corporation
- Robert F. Bartholomew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming semiconductor structure with improved isolation...
- Patent number 4,251,571
- Issue date Feb 17, 1981
- International Business Machines Corporation
- Paul L. Garbarino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Making semiconductor structure with improved phosphosilicate glass...
- Patent number 4,191,603
- Issue date Mar 4, 1980
- International Business Machines Corporation
- Paul L. Garbarino
- H01 - BASIC ELECTRIC ELEMENTS

Paul L. Garbarino

Person

Patents Grantslast 30 patents

Testing method and structure for leakage current characterization i...

Semiconductor structure with improved isolation between two layers...

Borderless diffusion contact process and structure

Method of making dense vertical FET's

FET Memory cell structure and process

Method for making an electrical contact to a silicon substrate thro...

Method for forming semiconductor structure with improved isolation...

Making semiconductor structure with improved phosphosilicate glass...