Paul M. Fuller

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Boise, ID, US

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Patents Grantslast 30 patents

Information Patent Grant
Timing calibration pattern for SLDRAM
- Patent number 6,889,357
- Issue date May 3, 2005
- Micron Technology, Inc.
- Brent Keeth
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed test system for a memory device
- Patent number 6,550,026
- Issue date Apr 15, 2003
- Micron Technology, Inc.
- Jeffrey P. Wright
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed test system for a memory device
- Patent number 6,154,860
- Issue date Nov 28, 2000
- Micron Technology, Inc.
- Jeffrey P. Wright
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for enabling redundant memory
- Patent number 6,055,611
- Issue date Apr 25, 2000
- Micron Technology, Inc.
- Jeffrey P. Wright
- G11 - INFORMATION STORAGE
Information Patent Grant
High-speed test system for a memory device
- Patent number 5,966,388
- Issue date Oct 12, 1999
- Micron Technology, Inc.
- Jeffrey P. Wright
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Timing calibration pattern for SLDRAM
- Publication number 20050185498
- Publication date Aug 25, 2005
- Brent Keeth
- H04 - ELECTRIC COMMUNICATION TECHNIQUE