Paul Michael Guglielmi

Person

Westboro, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performance optimization and system bus duty cycle reduction by I/O...
- Patent number 6,353,877
- Issue date Mar 5, 2002
- Compaq Computer Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance optimization and system bus duty cycle reduction by I/O...
- Patent number 6,128,711
- Issue date Oct 3, 2000
- Compaq Computer Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for providing DMA transfers between devices co...
- Patent number 6,012,120
- Issue date Jan 4, 2000
- Digital Equipment Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus providing DMA transfers between devices couple...
- Patent number 5,953,538
- Issue date Sep 14, 1999
- Digital Equipment Corporation
- Samuel Hammond Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch circuit and method with complementary clocking and level sens...
- Patent number 5,172,011
- Issue date Dec 15, 1992
- Digital Equipment Corporation
- Dale H. Leuthold
- G01 - MEASURING TESTING
Information Patent Grant
Self-timed random access memory chip
- Patent number 4,712,190
- Issue date Dec 8, 1987
- Digital Equipment Corporation
- Paul M. Guglielmi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory control system for transferring selected words in a multiple...
- Patent number 4,099,231
- Issue date Jul 4, 1978
- Digital Equipment Corporation
- Alan Kotok
- G06 - COMPUTING CALCULATING COUNTING

Paul Michael Guglielmi

Person

Patents Grantslast 30 patents

Performance optimization and system bus duty cycle reduction by I/O...

Performance optimization and system bus duty cycle reduction by I/O...

Method and apparatus for providing DMA transfers between devices co...

Method and apparatus providing DMA transfers between devices couple...

Latch circuit and method with complementary clocking and level sens...

Self-timed random access memory chip

Memory control system for transferring selected words in a multiple...