Paul R. Walling

Person

White Plains, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package metal shadowing checks
- Patent number 10,956,649
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Anson J. Call
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package floating metal checks
- Patent number 10,949,600
- Issue date Mar 16, 2021
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated generation of surface-mount package design
- Patent number 10,706,204
- Issue date Jul 7, 2020
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package via stack checking
- Patent number 10,546,096
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Anson J. Call
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package floating metal checks
- Patent number 10,423,751
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor package metal shadowing checks
- Patent number 10,423,752
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Anson J. Call
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk reduction between signal layers in a multilayered package...
- Patent number 10,375,820
- Issue date Aug 6, 2019
- International Business Machines Corporation
- Jinwoo Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk reduction between signal layers in a multilayered package...
- Patent number 9,955,567
- Issue date Apr 24, 2018
- International Business Machines Corporation
- Jinwoo Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk reduction between signal layers in a multilayered package...
- Patent number 8,927,879
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Jinwoo Choi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Elastic modulus mapping of a chip carrier in a flip chip package
- Patent number 8,756,546
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Erwin B. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nested design approach
- Patent number 7,325,213
- Issue date Jan 29, 2008
- International Business Machines Corporation
- Harsaran S. Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mesh plane generation and file storage
- Patent number 7,096,451
- Issue date Aug 22, 2006
- International Business Machines Corporation
- Alice L. Donaldson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substrate design of a chip using a generic substrate design
- Patent number 6,528,735
- Issue date Mar 4, 2003
- International Business Machines Corporation
- Harsaran S. Bhatia
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Direct deposit thin film single/multi chip module
- Patent number 6,261,467
- Issue date Jul 17, 2001
- International Business Machines Corporation
- Ajay P. Giri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct deposit thin film single/multi chip module
- Patent number 6,037,044
- Issue date Mar 14, 2000
- International Business Machines Corporation
- Ajay P. Giri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for designing a module
- Patent number 5,677,847
- Issue date Oct 14, 1997
- International Business Machines Corporation
- Paul R. Walling
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATED GENERATION OF SURFACE-MOUNT PACKAGE DESIGN
- Publication number 20200104454
- Publication date Apr 2, 2020
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS
- Publication number 20190377850
- Publication date Dec 12, 2019
- International Business Machines Corporation
- Anson J. Call
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS
- Publication number 20190362049
- Publication date Nov 28, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE VIA STACK CHECKING
- Publication number 20190102504
- Publication date Apr 4, 2019
- International Business Machines Corporation
- Anson J. Call
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS
- Publication number 20190102505
- Publication date Apr 4, 2019
- International Business Machines Corporation
- Jean Audet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS
- Publication number 20190102506
- Publication date Apr 4, 2019
- International Business Machines Corporation
- Anson J. Call
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...
- Publication number 20180213636
- Publication date Jul 26, 2018
- JINWOO CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...
- Publication number 20140331482
- Publication date Nov 13, 2014
- JINWOO CHOI
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE
- Publication number 20140033148
- Publication date Jan 30, 2014
- International Business Machines Corporation
- Erwin B. Cohen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...
- Publication number 20120125677
- Publication date May 24, 2012
- International Business Machines Corporation
- Jinwoo Choi
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
NESTED DESIGN APPROACH
- Publication number 20050278674
- Publication date Dec 15, 2005
- International Business Machines Corporation
- Harsaran S. Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MESH PLANE GENERATION AND FILE STORAGE
- Publication number 20050055660
- Publication date Mar 10, 2005
- Alice L. Donaldson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUBSTRATE DESIGN OF A CHIP USING A GENERIC SUBSTRATE DESIGN
- Publication number 20030047352
- Publication date Mar 13, 2003
- International Business Machines Corporation
- Harsaran S. Bhatia
- H01 - BASIC ELECTRIC ELEMENTS

Paul R. Walling

Person

Patents Grantslast 30 patents

Semiconductor package metal shadowing checks

Semiconductor package floating metal checks

Automated generation of surface-mount package design

Semiconductor package via stack checking

Semiconductor package floating metal checks

Semiconductor package metal shadowing checks

Crosstalk reduction between signal layers in a multilayered package...

Crosstalk reduction between signal layers in a multilayered package...

Crosstalk reduction between signal layers in a multilayered package...

Elastic modulus mapping of a chip carrier in a flip chip package

Nested design approach

Mesh plane generation and file storage

Substrate design of a chip using a generic substrate design

Direct deposit thin film single/multi chip module

Direct deposit thin film single/multi chip module

Method and apparatus for designing a module

Patents Applicationslast 30 patents

AUTOMATED GENERATION OF SURFACE-MOUNT PACKAGE DESIGN

SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS

SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS

SEMICONDUCTOR PACKAGE VIA STACK CHECKING

SEMICONDUCTOR PACKAGE FLOATING METAL CHECKS

SEMICONDUCTOR PACKAGE METAL SHADOWING CHECKS

CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...

CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...

ELASTIC MODULUS MAPPING OF A CHIP CARRIER IN A FLIP CHIP PACKAGE

CROSSTALK REDUCTION BETWEEN SIGNAL LAYERS IN A MULTILAYERED PACKAGE...

NESTED DESIGN APPROACH

MESH PLANE GENERATION AND FILE STORAGE

SUBSTRATE DESIGN OF A CHIP USING A GENERIC SUBSTRATE DESIGN