Paul Smith

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and structure for utilizing external interfaces used during...
- Patent number 8,745,457
- Issue date Jun 3, 2014
- LSI Corporation
- Eugene Saghi
- G01 - MEASURING TESTING
Information Patent Grant
Methods and structure for correlation of test signals routed using...
- Patent number 8,738,979
- Issue date May 27, 2014
- LSI Corporation
- Paul J. Smith
- G01 - MEASURING TESTING
Information Patent Grant
Configurable reset circuit for a phase-locked loop
- Patent number 7,719,368
- Issue date May 18, 2010
- Agere Systems Inc.
- Paul Jeffrey Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits and associated methods for improved debug and test of an a...
- Patent number 7,617,428
- Issue date Nov 10, 2009
- LSI Corporation
- Paul J. Smith
- G01 - MEASURING TESTING
Information Patent Grant
Characteristic image of electrical data bus
- Patent number 7,028,233
- Issue date Apr 11, 2006
- LSI Logic Corporation
- Andrew Hadley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multi-channel data delay equalization
- Patent number 6,647,027
- Issue date Nov 11, 2003
- LSI Logic Corporation
- Frank Gasparik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for measuring delay of digital signal using clock generator...
- Patent number 6,560,716
- Issue date May 6, 2003
- LSI Logic Corporation
- Frank Gasparik
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
IO power management: synchronously regulated output skew
- Patent number 6,459,313
- Issue date Oct 1, 2002
- LSI Logic Corporation
- Joy F. Godbee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spare cells placement methodology
- Patent number 6,446,248
- Issue date Sep 3, 2002
- LSI Logic Corporation
- Richard L. Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for programmable chip initialization
- Patent number 6,292,409
- Issue date Sep 18, 2001
- LSI Logic Corporation
- Paul J. Smith
- G11 - INFORMATION STORAGE
Information Patent Grant
Test mode for multifunction PCI device
- Patent number 5,905,744
- Issue date May 18, 1999
- LSI Logic Corporation
- Brian G. Reise
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory input data test arrangement
- Patent number 5,077,690
- Issue date Dec 31, 1991
- Atmel Corporation
- Paul J. Smith
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND STRUCTURE FOR CORRELATION OF TEST SIGNALS ROUTED USING...
- Publication number 20130262946
- Publication date Oct 3, 2013
- Paul J. Smith
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND STRUCTURE FOR UTILIZING EXTERNAL INTERFACES USED DURING...
- Publication number 20130257512
- Publication date Oct 3, 2013
- Eugene Saghi
- G01 - MEASURING TESTING
Information Patent Application
CONFIGURABLE RESET CIRCUIT FOR A PHASE-LOCKED LOOP
- Publication number 20100124256
- Publication date May 20, 2010
- Paul Jeffrey Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuits and associated methods for improved debug and test of an a...
- Publication number 20080052574
- Publication date Feb 28, 2008
- LSI Logic Corporation
- Paul J. Smith
- G01 - MEASURING TESTING
Information Patent Application
Systems and methods for opportunistic frame queue management in SAS...
- Publication number 20060080671
- Publication date Apr 13, 2006
- Brian A. Day
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Characteristic image of electrical data bus
- Publication number 20040133835
- Publication date Jul 8, 2004
- Andrew Hadley
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Methods and structure for utilizing external interfaces used during...

Methods and structure for correlation of test signals routed using...

Configurable reset circuit for a phase-locked loop

Circuits and associated methods for improved debug and test of an a...

Characteristic image of electrical data bus

Method and apparatus for multi-channel data delay equalization

System for measuring delay of digital signal using clock generator...

IO power management: synchronously regulated output skew

Spare cells placement methodology

System for programmable chip initialization

Test mode for multifunction PCI device

Memory input data test arrangement

Patents Applicationslast 30 patents

METHODS AND STRUCTURE FOR CORRELATION OF TEST SIGNALS ROUTED USING...

METHODS AND STRUCTURE FOR UTILIZING EXTERNAL INTERFACES USED DURING...

CONFIGURABLE RESET CIRCUIT FOR A PHASE-LOCKED LOOP

Circuits and associated methods for improved debug and test of an a...

Systems and methods for opportunistic frame queue management in SAS...

Characteristic image of electrical data bus