Pavan Lanka

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Folsom, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for a highly efficient graphics processing uni...
- Patent number 10,521,874
- Issue date Dec 31, 2019
- Intel Corporation
- Jayanth N. Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Facilitating dynamic pipelining of workload executions on graphics...
- Patent number 10,068,306
- Issue date Sep 4, 2018
- Intel Corporation
- Jayanth N. Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sharing non-page aligned memory
- Patent number 9,478,000
- Issue date Oct 25, 2016
- Intel Corporation
- Jayanth Rao
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EMPLOYING OUT OF ORDER QUEUES FOR BETTER GPU UTILIZATION
- Publication number 20170300361
- Publication date Oct 19, 2017
- Intel Corporation
- Pavan K. Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FACILITATING DYNAMIC PIPELINING OF WORKLOAD EXECUTIONS ON GRAPHICS...
- Publication number 20160180486
- Publication date Jun 23, 2016
- Intel Corporation
- JAYANTH N. RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A HIGHLY EFFICIENT GRAPHICS PROCESSING UNI...
- Publication number 20160093012
- Publication date Mar 31, 2016
- Intel Corporation
- JAYANTH N. RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING NON-PAGE ALIGNED MEMORY
- Publication number 20150091924
- Publication date Apr 2, 2015
- Jayanth Rao
- G06 - COMPUTING CALCULATING COUNTING