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Pawan Kulshreshtha
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San Jose, CA, US
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Patents Grants
last 30 patents
Information
Patent Grant
Systems and methods for calculating common clock path pessimism for...
Patent number
10,467,365
Issue date
Nov 5, 2019
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
System and method for generating reduced standard delay format file...
Patent number
10,460,059
Issue date
Oct 29, 2019
Cadence Design Systems, Inc.
Akash Khandelwal
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Timing context generation with multi-instance blocks for hierarchic...
Patent number
10,169,501
Issue date
Jan 1, 2019
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Methods, systems, and articles of manufacture for multi-mode, multi...
Patent number
10,133,842
Issue date
Nov 20, 2018
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Hierarchical timing analysis for multi-instance blocks
Patent number
10,037,394
Issue date
Jul 31, 2018
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
System and method for common path pessimism reduction in timing ana...
Patent number
8,745,561
Issue date
Jun 3, 2014
Cadence Design Systems, Inc.
Vibhor Garg
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Transistor-level timing analysis using embedded simulation
Patent number
7,647,220
Issue date
Jan 12, 2010
Cadence Design Systems, Inc.
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
Transistor-level timing analysis using embedded simulation
Publication number
20030115035
Publication date
Jun 19, 2003
Pawan Kulshreshtha
G06 - COMPUTING CALCULATING COUNTING