Pedja Raspopovic

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for adaptive timing optimization of an integra...
- Patent number 7,020,589
- Issue date Mar 28, 2006
- LSI Logic Corporation
- Partha P. Datta Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual tree-based netlist model and method of delay estimation for...
- Patent number 6,643,832
- Issue date Nov 4, 2003
- LSI Logic Corporation
- Partha P. Data Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist resynthesis program based on physical delay calculation
- Patent number 6,557,144
- Issue date Apr 29, 2003
- LSI Logic Corporation
- Aiguo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Netlist resynthesis program using structure co-factoring
- Patent number 6,546,539
- Issue date Apr 8, 2003
- LSI Logic Corporation
- Aiquo Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Channel router with buffer insertion
- Patent number 6,505,336
- Issue date Jan 7, 2003
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC timing analysis with known false paths
- Patent number 6,463,572
- Issue date Oct 8, 2002
- LSI Logic Corporation
- Ivan Pavisic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process for solving assignment problems in integrated circuit desig...
- Patent number 6,453,453
- Issue date Sep 17, 2002
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wire routing optimization
- Patent number 6,412,102
- Issue date Jun 25, 2002
- LSI Logic Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for parallel simultaneous global and detail ro...
- Patent number 6,324,674
- Issue date Nov 27, 2001
- LSI Logic Corporation
- Alexander E. Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for local optimization of the global routing
- Patent number 6,289,495
- Issue date Sep 11, 2001
- LSI Logic Corporation
- Pedja Raspopovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for parallel routing locking mechanism
- Patent number 6,269,469
- Issue date Jul 31, 2001
- LSI Logic Corporation
- Ivan Pavisic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for coarse global routing
- Patent number 6,260,183
- Issue date Jul 10, 2001
- LSI Logic Corporation
- Pedja Raspopovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Net routing using basis element decomposition
- Patent number 6,253,363
- Issue date Jun 26, 2001
- LSI Logic Corporation
- Elyar E. Gasanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for parallel Steiner tree routing
- Patent number 6,247,167
- Issue date Jun 12, 2001
- LSI Logic Corporation
- Pedja Raspopovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for minimization of process defects while routing
- Patent number 6,230,306
- Issue date May 8, 2001
- LSI Logic Corporation
- Pedja Raspopovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal layer assignment
- Patent number 6,182,272
- Issue date Jan 30, 2001
- LSI Logic Corporation
- Alexander Andreev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for hierarchical global routing descend
- Patent number 6,175,950
- Issue date Jan 16, 2001
- LSI Logic Corporation
- Ranko Scepanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-saving method and apparatus for partitioning high fanout nets
- Patent number 6,154,874
- Issue date Nov 28, 2000
- LSI Logic Corporation
- Ranko Scepanovic
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR PARALLEL SIMULTANEOUS GLOBAL AND DETAIL RO...
- Publication number 20010018759
- Publication date Aug 30, 2001
- ALEXANDER E. ANDREEV
- G06 - COMPUTING CALCULATING COUNTING

Pedja Raspopovic

Person

Patents Grantslast 30 patents

Method and apparatus for adaptive timing optimization of an integra...

Virtual tree-based netlist model and method of delay estimation for...

Netlist resynthesis program based on physical delay calculation

Netlist resynthesis program using structure co-factoring

Channel router with buffer insertion

IC timing analysis with known false paths

Process for solving assignment problems in integrated circuit desig...

Wire routing optimization

Method and apparatus for parallel simultaneous global and detail ro...

Method and apparatus for local optimization of the global routing

Method and apparatus for parallel routing locking mechanism

Method and apparatus for coarse global routing

Net routing using basis element decomposition

Method and apparatus for parallel Steiner tree routing

Method and apparatus for minimization of process defects while routing

Metal layer assignment

Method and apparatus for hierarchical global routing descend

Memory-saving method and apparatus for partitioning high fanout nets

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR PARALLEL SIMULTANEOUS GLOBAL AND DETAIL RO...