Peeyoosh Nitin Mirajkar

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Kolhapur, IN

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Patents Grantslast 30 patents

Information Patent Grant
Glitch-free synchronization and SYSREF windowing and generation scheme
- Patent number 11,977,407
- Issue date May 7, 2024
- Texas Instruments Incorporated
- Apoorva Bhatia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-PFD feedback delay generation circuit
- Patent number 10,439,620
- Issue date Oct 8, 2019
- Texas Instruments Incorporated
- Theertham Srinivas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase syncronizing PLL output across reference and VCO clock domains
- Patent number 10,243,573
- Issue date Mar 26, 2019
- Texas Instruments Incorporated
- Jagdish Chand Goyal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase frequency detector (PFD) circuit with improved lock time
- Patent number 9,503,105
- Issue date Nov 22, 2016
- Texas Instruments Incorporated
- Peeyoosh Nitin Mirajkar
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DETERMINISTIC JITTER COMPENSATION SCHEME FOR DTC TIMING PATH
- Publication number 20240113716
- Publication date Apr 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Yogesh DARWHEKAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
GLITCH-FREE SYNCHRONIZATION AND SYSREF WINDOWING AND GENERATION SCHEME
- Publication number 20220382320
- Publication date Dec 1, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Apoorva BHATIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-PFD FEEDBACK DELAY GENERATION CIRCUIT
- Publication number 20180091157
- Publication date Mar 29, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Theertham Srinivas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE FREQUENCY DETECTOR (PFD) CIRCUIT WITH IMPROVED LOCK TIME
- Publication number 20160112055
- Publication date Apr 21, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Peeyoosh Nitin Mirajkar
- H03 - BASIC ELECTRONIC CIRCUITRY