Pei-Hsin Ho

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Predictor-guided cell spreader to improve routability for designs a...
- Patent number 11,194,949
- Issue date Dec 7, 2021
- Synopsys, Inc.
- Prashant Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Priori corner and mode reduction
- Patent number 9,141,742
- Issue date Sep 22, 2015
- Synopsys, Inc.
- Jeng-Liang Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-mode redundancy removal
- Patent number 8,266,563
- Issue date Sep 11, 2012
- Synopsys, Inc.
- Stephen M. Plaza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for proximate placement of sequential cells
- Patent number 8,099,702
- Issue date Jan 17, 2012
- Synopsys, Inc.
- Wenting Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for determining the timing of an integrated ci...
- Patent number 7,984,405
- Issue date Jul 19, 2011
- Synopsys, Inc.
- Yiu Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating a boolean SAT solver into a router
- Patent number 7,904,867
- Issue date Mar 8, 2011
- Synopsys, Inc.
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect-driven physical synthesis using persistent virtual rou...
- Patent number 7,853,915
- Issue date Dec 14, 2010
- Synopsys, Inc.
- Prashant Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating a variation-tolerant clock-tree...
- Patent number 7,546,567
- Issue date Jun 9, 2009
- Synopsys, Inc.
- Yongseok Cheon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Abstraction refinement using controllability and cooperativeness an...
- Patent number 7,469,392
- Issue date Dec 23, 2008
- Synopsys, Inc.
- Yiu Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and Apparatus for Solving Sequential Constraints
- Patent number 7,454,727
- Issue date Nov 18, 2008
- Synopsys, Inc.
- Eduard Cerny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for partitioning an integrated circuit chip
- Patent number 7,260,802
- Issue date Aug 21, 2007
- Synopsys, Inc.
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing power consumption in an integrate...
- Patent number 7,257,782
- Issue date Aug 14, 2007
- Synopsys, Inc.
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation-based functional verification of microcircuit designs
- Patent number 7,130,783
- Issue date Oct 31, 2006
- Synopsys, Inc.
- Kevin M. Harer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for solving sequential constraints
- Patent number 7,076,753
- Issue date Jul 11, 2006
- Synopsys, Inc.
- Eduard Cerny
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRIORI CORNER AND MODE REDUCTION
- Publication number 20140189634
- Publication date Jul 3, 2014
- Synopsys, Inc.
- Jeng-Liang Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Mode Redundancy Removal
- Publication number 20110126167
- Publication date May 26, 2011
- Synopsys, Inc.
- Stephen M. Plaza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Proximate Placement of Sequential Cells
- Publication number 20100031214
- Publication date Feb 4, 2010
- Synopsys, Inc.
- Wenting Hou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interconnect-Driven Physical Synthesis Using Persistent Virtual Rou...
- Publication number 20090319977
- Publication date Dec 24, 2009
- Synopsys, Inc.
- Prashant Saxena
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrating a boolean SAT solver into a router
- Publication number 20080250376
- Publication date Oct 9, 2008
- Jerry R. Burch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DETERMINING THE TIMING OF AN INTEGRATED CI...
- Publication number 20080168411
- Publication date Jul 10, 2008
- Synopsys, Inc.
- Yiu-Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for generating a variation-tolerant clock-tree...
- Publication number 20080168412
- Publication date Jul 10, 2008
- Yongseok Cheon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Abstraction refinement using controllability and cooperativeness an...
- Publication number 20060129959
- Publication date Jun 15, 2006
- Yiu Chung Mang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for partitioning an integrated circuit chip
- Publication number 20060101365
- Publication date May 11, 2006
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing power consumption in an integrate...
- Publication number 20060090153
- Publication date Apr 27, 2006
- Pei-Hsin Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for solving sequential constraints
- Publication number 20050138585
- Publication date Jun 23, 2005
- Eduard Cerny
- G06 - COMPUTING CALCULATING COUNTING

Pei-Hsin Ho

Person

Patents Grantslast 30 patents

Predictor-guided cell spreader to improve routability for designs a...

Priori corner and mode reduction

Multi-mode redundancy removal

Method and apparatus for proximate placement of sequential cells

Method and apparatus for determining the timing of an integrated ci...

Integrating a boolean SAT solver into a router

Interconnect-driven physical synthesis using persistent virtual rou...

Method and apparatus for generating a variation-tolerant clock-tree...

Abstraction refinement using controllability and cooperativeness an...

Method and Apparatus for Solving Sequential Constraints

Method and apparatus for partitioning an integrated circuit chip

Method and apparatus for reducing power consumption in an integrate...

Simulation-based functional verification of microcircuit designs

Method and apparatus for solving sequential constraints

Patents Applicationslast 30 patents

PRIORI CORNER AND MODE REDUCTION

Multi-Mode Redundancy Removal

Method and Apparatus for Proximate Placement of Sequential Cells

Interconnect-Driven Physical Synthesis Using Persistent Virtual Rou...

Integrating a boolean SAT solver into a router

METHOD AND APPARATUS FOR DETERMINING THE TIMING OF AN INTEGRATED CI...

Method and apparatus for generating a variation-tolerant clock-tree...

Abstraction refinement using controllability and cooperativeness an...

Method and apparatus for partitioning an integrated circuit chip

Method and apparatus for reducing power consumption in an integrate...

Method and apparatus for solving sequential constraints