Pei-Ying Hsueh

Person

Changhua County, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Test device for testing on-chip clock controller having debug function
- Patent number 12,320,847
- Issue date Jun 3, 2025
- Realtek Semiconductor Corporation
- Sheng-Ping Yung
- G01 - MEASURING TESTING
Information Patent Grant
Clock control circuit and method
- Patent number 12,320,849
- Issue date Jun 3, 2025
- Realtek Semiconductor Corporation
- Yu-Ting Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Isolation circuit having test mechanism and test method thereof
- Patent number 11,774,497
- Issue date Oct 3, 2023
- Realtek Semiconductor Corporation
- Kuo-Kai Liu
- G01 - MEASURING TESTING
Information Patent Grant
Chip and testing method thereof
- Patent number 11,287,472
- Issue date Mar 29, 2022
- Realtek Semiconductor Corporation
- Sheng-Ping Yung
- G01 - MEASURING TESTING
Information Patent Grant
Chip
- Patent number 10,698,029
- Issue date Jun 30, 2020
- Realtek Semiconductor Corp.
- Sheng-Ping Yung
- G01 - MEASURING TESTING
Information Patent Grant
Multiple defect diagnosis method and machine readable media
- Patent number 9,983,264
- Issue date May 29, 2018
- Realtek Semiconductor Corp.
- Pei-Ying Hsueh
- G01 - MEASURING TESTING
Information Patent Grant
Systematic defect analysis method and machine readable media
- Patent number 9,213,799
- Issue date Dec 15, 2015
- Realtek Semiconductor Corp.
- Pei-Ying Hsueh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CLOCK CONTROL CIRCUIT AND METHOD
- Publication number 20250035702
- Publication date Jan 30, 2025
- REALTEK SEMICONDUCTOR CORPORATION
- Yu-Ting LI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Test device for testing on-chip clock controller having debug function
- Publication number 20240230757
- Publication date Jul 11, 2024
- REALTEK SEMICONDUCTOR CORPORATION
- SHENG-PING YUNG
- G01 - MEASURING TESTING
Information Patent Application
Test device for testing on-chip clock controller having debug function
- Publication number 20240133950
- Publication date Apr 25, 2024
- REALTEK SEMICONDUCTOR CORPORATION
- SHENG-PING YUNG
- G01 - MEASURING TESTING
Information Patent Application
Isolation circuit having test mechanism and test method thereof
- Publication number 20220120812
- Publication date Apr 21, 2022
- REALTEK SEMICONDUCTOR CORPORATION
- KUO-KAI LIU
- G01 - MEASURING TESTING
Information Patent Application
CHIP AND TESTING METHOD THEREOF
- Publication number 20210096180
- Publication date Apr 1, 2021
- REALTEK SEMICONDUCTOR CORPORATION
- Sheng-Ping YUNG
- G01 - MEASURING TESTING
Information Patent Application
CHIP
- Publication number 20200124666
- Publication date Apr 23, 2020
- Realtek Semiconductor Corp.
- Sheng-Ping Yung
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE DEFECT DIAGNOSIS METHOD AND MACHINE READABLE MEDIA
- Publication number 20150204939
- Publication date Jul 23, 2015
- Realtek Semiconductor Corp.
- Pei-Ying Hsueh
- G01 - MEASURING TESTING
Information Patent Application
SYSTEMATIC DEFECT ANALYSIS METHOD AND MACHINE READABLE MEDIA
- Publication number 20150205907
- Publication date Jul 23, 2015
- Realtek Semiconductor Corp.
- Pei-Ying Hsueh
- G06 - COMPUTING CALCULATING COUNTING

Pei-Ying Hsueh

Person

Patents Grantslast 30 patents

Test device for testing on-chip clock controller having debug function

Clock control circuit and method

Isolation circuit having test mechanism and test method thereof

Chip and testing method thereof

Chip

Multiple defect diagnosis method and machine readable media

Systematic defect analysis method and machine readable media

Patents Applicationslast 30 patents

CLOCK CONTROL CIRCUIT AND METHOD

Test device for testing on-chip clock controller having debug function

Test device for testing on-chip clock controller having debug function

Isolation circuit having test mechanism and test method thereof

CHIP AND TESTING METHOD THEREOF

CHIP

MULTIPLE DEFECT DIAGNOSIS METHOD AND MACHINE READABLE MEDIA

SYSTEMATIC DEFECT ANALYSIS METHOD AND MACHINE READABLE MEDIA