Pei-Yuan Gao

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low-H plasma treatment with N2 anneal for electronic memory devices
- Patent number 8,202,810
- Issue date Jun 19, 2012
- Spansion LLC
- Alexander H. Nickel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interlayer dielectric for charge loss improvement
- Patent number 7,300,886
- Issue date Nov 27, 2007
- Spansion LLC
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory with data retention liner
- Patent number 7,297,592
- Issue date Nov 20, 2007
- Spansion LLC
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a hardmask employing multiple independently form...
- Patent number 7,183,198
- Issue date Feb 27, 2007
- Advanced Micro Devices, Inc.
- Pei-Yuan Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PECVD silicon-rich oxide layer for reduced UV charging
- Patent number 7,060,554
- Issue date Jun 13, 2006
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chamber deposition of silicon oxynitride film for patterning
- Patent number 7,033,960
- Issue date Apr 25, 2006
- Advanced Micro Devices, Inc.
- Lu You
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Undoped oxide liner/BPSG for improved data retention
- Patent number 7,023,046
- Issue date Apr 4, 2006
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Liner for semiconductor memories and manufacturing method therefor
- Patent number 6,803,265
- Issue date Oct 12, 2004
- FASL LLC
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a hardmask employing multiple independently form...
- Patent number 6,803,313
- Issue date Oct 12, 2004
- Advanced Micro Devices, Inc.
- Pei-Yuan Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing pattern deformation and photoresist poisoning i...
- Patent number 6,764,949
- Issue date Jul 20, 2004
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CVD silicon carbide layer as a BARC and hard mask for gate patterning
- Patent number 6,653,735
- Issue date Nov 25, 2003
- Advanced Micro Devices, Inc.
- Chih Yuh Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory...
- Patent number 6,627,973
- Issue date Sep 30, 2003
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of forming a void-free interlayer dielectric (ILD0) for 0.18...
- Patent number 6,489,253
- Issue date Dec 3, 2002
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of depositing sion with reduced defects
- Patent number 6,410,461
- Issue date Jun 25, 2002
- Advanced Micro Devices, Inc.
- Pei-Yuan Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of inspecting a semiconductor wafer for defects
- Patent number 6,403,385
- Issue date Jun 11, 2002
- Advanced Micro Devices, Inc.
- Subramanian Venkatkrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor wafer for measurement and recordation of impurities i...
- Patent number 6,369,453
- Issue date Apr 9, 2002
- Advanced Micro Devices, Inc.
- Pei-Yuan Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to rework device with faulty metal stack layer
- Patent number 6,297,065
- Issue date Oct 2, 2001
- Advanced Micro Devices, Inc.
- Jiahua Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES
- Publication number 20090176369
- Publication date Jul 9, 2009
- Alexander H. Nickel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method of fabricating the same
- Publication number 20060214218
- Publication date Sep 28, 2006
- Kiyokazu Shishido
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hardmask employing multiple layers of silicon oxynitride
- Publication number 20050048771
- Publication date Mar 3, 2005
- Advanced Micro Devices, Inc.
- Pei-Yuan Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Undoped oxide liner/BPSG for improved data retention
- Publication number 20050006693
- Publication date Jan 13, 2005
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Hardmask employing multiple layers of silicon oxynitride
- Publication number 20040061227
- Publication date Apr 1, 2004
- Advanced Micro Devices, Inc.
- Pei-Yuan Gao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing pattern deformation and photoresist poisoning i...
- Publication number 20040023475
- Publication date Feb 5, 2004
- Advanced Micro Devices, Inc.
- Douglas J. Bonser
- H01 - BASIC ELECTRIC ELEMENTS

Pei-Yuan Gao

Person

Patents Grantslast 30 patents

Low-H plasma treatment with N2 anneal for electronic memory devices

Interlayer dielectric for charge loss improvement

Semiconductor memory with data retention liner

Method for forming a hardmask employing multiple independently form...

PECVD silicon-rich oxide layer for reduced UV charging

Multi-chamber deposition of silicon oxynitride film for patterning

Undoped oxide liner/BPSG for improved data retention

Liner for semiconductor memories and manufacturing method therefor

Method for forming a hardmask employing multiple independently form...

Method for reducing pattern deformation and photoresist poisoning i...

CVD silicon carbide layer as a BARC and hard mask for gate patterning

Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory...

Method of forming a void-free interlayer dielectric (ILD0) for 0.18...

Method of depositing sion with reduced defects

Method of inspecting a semiconductor wafer for defects

Semiconductor wafer for measurement and recordation of impurities i...

Method to rework device with faulty metal stack layer

Patents Applicationslast 30 patents

LOW-H PLASMA TREATMENT WITH N2 ANNEAL FOR ELECTRONIC MEMORY DEVICES

Semiconductor device and method of fabricating the same

Hardmask employing multiple layers of silicon oxynitride

Undoped oxide liner/BPSG for improved data retention

Hardmask employing multiple layers of silicon oxynitride

Method for reducing pattern deformation and photoresist poisoning i...