Peidong Wang

Person

Suzhou, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Level shifter spare cell
- Patent number 10,475,780
- Issue date Nov 12, 2019
- NXP USA, INC.
- Zhe Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low leakage isolation cell
- Patent number 10,263,619
- Issue date Apr 16, 2019
- NXP USA, INC.
- Peidong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with multi-bit clock gating cells
- Patent number 9,838,013
- Issue date Dec 5, 2017
- NXP USA, INC.
- Zhe Ge
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-bit flip-flop with shared clock switch
- Patent number 9,755,623
- Issue date Sep 5, 2017
- NXP USA, INC.
- Zhihong Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop circuit with resistive poly routing
- Patent number 9,148,149
- Issue date Sep 29, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Zhihong Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
State retention power gated cell
- Patent number 8,987,786
- Issue date Mar 24, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Miaolin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System for optimizing number of dies produced on a wafer
- Patent number 8,671,381
- Issue date Mar 11, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Peidong Wang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
LOW LEAKAGE ISOLATION CELL
- Publication number 20190140642
- Publication date May 9, 2019
- NXP USA, Inc.
- Peidong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL SHIFTER SPARE CELL
- Publication number 20190067263
- Publication date Feb 28, 2019
- NXP USA, Inc.
- Zhe Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH MULTI-BIT CLOCK GATING CELLS
- Publication number 20170302277
- Publication date Oct 19, 2017
- NXP USA, Inc.
- Zhe Ge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT USING STANDARD CELLS FROM TWO OR MORE LIBRARIES
- Publication number 20170116365
- Publication date Apr 27, 2017
- FREESCALE SEMICONDUCTOR, INC.
- ZHIHONG CHENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-BIT FLIP-FLOP WITH SHARED CLOCK SWITCH
- Publication number 20170063350
- Publication date Mar 2, 2017
- FREESCALE SEMICONDUCTOR, INC.
- ZHIHONG CHENG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STATE RETENTION POWER GATED CELL
- Publication number 20150091626
- Publication date Apr 2, 2015
- Miaolin Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STATE RETENTION POWER GATED CELL FOR INTEGRATED CIRCUIT
- Publication number 20150084680
- Publication date Mar 26, 2015
- Zhihong Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FLIP-FLOP CIRCUIT WITH RESISTIVE POLY ROUTING
- Publication number 20140285236
- Publication date Sep 25, 2014
- Zhihong Cheng
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM FOR OPTIMIZING NUMBER OF DIES PRODUCED ON A WAFER
- Publication number 20140096103
- Publication date Apr 3, 2014
- Peidong Wang
- G06 - COMPUTING CALCULATING COUNTING

Peidong Wang

Person

Patents Grantslast 30 patents

Level shifter spare cell

Low leakage isolation cell

Integrated circuit with multi-bit clock gating cells

Multi-bit flip-flop with shared clock switch

Flip-flop circuit with resistive poly routing

State retention power gated cell

System for optimizing number of dies produced on a wafer

Patents Applicationslast 30 patents

LOW LEAKAGE ISOLATION CELL

LEVEL SHIFTER SPARE CELL

INTEGRATED CIRCUIT WITH MULTI-BIT CLOCK GATING CELLS

INTEGRATED CIRCUIT USING STANDARD CELLS FROM TWO OR MORE LIBRARIES

MULTI-BIT FLIP-FLOP WITH SHARED CLOCK SWITCH

STATE RETENTION POWER GATED CELL

STATE RETENTION POWER GATED CELL FOR INTEGRATED CIRCUIT

FLIP-FLOP CIRCUIT WITH RESISTIVE POLY ROUTING

SYSTEM FOR OPTIMIZING NUMBER OF DIES PRODUCED ON A WAFER