Perumal Ratnam

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Barrier modulated cell structures with intrinsic vertical bit line...
- Patent number 10,388,870
- Issue date Aug 20, 2019
- SanDisk Technologies LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-gate vertical field effect transistor with channel strips lat...
- Patent number 10,032,908
- Issue date Jul 24, 2018
- SanDisk Technologies LLC
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory hole bit line structures
- Patent number 9,922,709
- Issue date Mar 20, 2018
- SanDisk Technologies LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional memory device with vertical semiconductor bit lin...
- Patent number 9,859,337
- Issue date Jan 2, 2018
- SanDisk Technologies LLC
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistive three-dimensional memory device with heterostructure semi...
- Patent number 9,818,801
- Issue date Nov 14, 2017
- SanDisk Technologies LLC
- Peter Rabkin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reversible resistivity memory with crystalline silicon bit line
- Patent number 9,685,484
- Issue date Jun 20, 2017
- SanDisk Technologies LLC
- Peter Rabkin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low forming voltage non-volatile storage device
- Patent number 9,576,660
- Issue date Feb 21, 2017
- SanDisk Technologies LLC
- Zhida Lan
- G11 - INFORMATION STORAGE
Information Patent Grant
Intrinsic vertical bit line architecture
- Patent number 9,484,092
- Issue date Nov 1, 2016
- SanDisk Technologies LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling adjustable resistance bit lines connected to word line...
- Patent number 9,484,093
- Issue date Nov 1, 2016
- SanDisk Technologies LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Setting channel voltages of adjustable resistance bit line structur...
- Patent number 9,455,301
- Issue date Sep 27, 2016
- SanDisk Technologies LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Side wall bit line structures
- Patent number 9,373,396
- Issue date Jun 21, 2016
- SanDisk Technologies Inc.
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Vertical memory cells and methods of operation
- Patent number 9,355,736
- Issue date May 31, 2016
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Low forming voltage non-volatile storage device
- Patent number 9,269,425
- Issue date Feb 23, 2016
- Sandisk 3D LLC
- Zhida Lan
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared-gate vertical-TFT for vertical bit line array
- Patent number 9,236,122
- Issue date Jan 12, 2016
- Sandisk 3D LLC
- Tianhong Yan
- G11 - INFORMATION STORAGE
Information Patent Grant
Vertical memory cells and methods, architectures and devices for th...
- Patent number 8,885,407
- Issue date Nov 11, 2014
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Photodiode for multiple wavelength operation
- Patent number 7,956,432
- Issue date Jun 7, 2011
- Intersil Americas Inc.
- Dong Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for erasing an erasable programmable read only memory (E...
- Patent number 6,456,537
- Issue date Sep 24, 2002
- Alliance Semiconductor
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EPROM memory cell having increased capacitive coupling and me...
- Patent number 6,429,076
- Issue date Aug 6, 2002
- Alliance Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having reduced source leakage during source erase
- Patent number 6,303,959
- Issue date Oct 16, 2001
- Alliance Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique to improve the source leakage of flash EPROM cells during...
- Patent number 6,236,608
- Issue date May 22, 2001
- Alliance Semiconductor
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash EPROM memory cell having increased capacitive coupling
- Patent number 6,166,409
- Issue date Dec 26, 2000
- Alliance Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of and apparatus for increasing load resistance within an SR...
- Patent number 5,986,922
- Issue date Nov 16, 1999
- Alliance Semiconductor
- Ratnam Perumal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Making walled emitter bipolar transistor with reduced base narrowing
- Patent number 5,338,695
- Issue date Aug 16, 1994
- National Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
BARRIER MODULATED CELL STRUCTURES WITH INTRINSIC VERTICAL BIT LINE...
- Publication number 20190123276
- Publication date Apr 25, 2019
- SanDisk Technologies LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-GATE VERTICAL FIELD EFFECT TRANSISTOR WITH CHANNEL STRIPS LAT...
- Publication number 20180197988
- Publication date Jul 12, 2018
- SanDisk Technologies LLC
- Perumal RATNAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL SEMICONDUCTOR BIT LIN...
- Publication number 20170250224
- Publication date Aug 31, 2017
- SanDisk Technologies LLC
- Perumal RATNAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE
- Publication number 20160133325
- Publication date May 12, 2016
- SanDisk 3D LLC
- Zhida Lan
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING DISTURB WITH ADJUSTABLE RESISTANCE BIT LINE STRUCTURES
- Publication number 20160019957
- Publication date Jan 21, 2016
- SanDisk 3D LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Application
INTRINSIC VERTICAL BIT LINE ARCHITECTURE
- Publication number 20160019952
- Publication date Jan 21, 2016
- SanDisk 3D LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATION MODES FOR ADJUSTABLE RESISTANCE BIT LINE STRUCTURES
- Publication number 20160019960
- Publication date Jan 21, 2016
- SanDisk 3D LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING ADJUSTABLE RESISTANCE BIT LINES CONNECTED TO WORD LINE...
- Publication number 20160019961
- Publication date Jan 21, 2016
- SanDisk 3D LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Application
SIDE WALL BIT LINE STRUCTURES
- Publication number 20160020389
- Publication date Jan 21, 2016
- SanDisk 3D LLC
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY HOLE BIT LINE STRUCTURES
- Publication number 20160020255
- Publication date Jan 21, 2016
- SanDisk 3D LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Application
SETTING CHANNEL VOLTAGES USING A DUMMY WORD LINE
- Publication number 20160019953
- Publication date Jan 21, 2016
- SanDisk 3D LLC
- Perumal Ratnam
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY
- Publication number 20150036414
- Publication date Feb 5, 2015
- SANDISK 3D, LLC
- Tianhong Yan
- G11 - INFORMATION STORAGE
Information Patent Application
LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE
- Publication number 20130170283
- Publication date Jul 4, 2013
- SanDisk 3D LLC
- Zhida Lan
- G11 - INFORMATION STORAGE
Information Patent Application
SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR...
- Publication number 20130011985
- Publication date Jan 10, 2013
- PERUMAL RATNAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR...
- Publication number 20120273882
- Publication date Nov 1, 2012
- PERUMAL RATNAM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTODIODE FOR MULTIPLE WAVELENGTH OPERATION
- Publication number 20090174021
- Publication date Jul 9, 2009
- Intersil Americas Inc.
- Dong Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Photodiodes with anti-reflection coating
- Publication number 20060214251
- Publication date Sep 28, 2006
- Intersil Americas Inc.
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash eprom memory cell having increased capacitive coupling and me...
- Publication number 20010015920
- Publication date Aug 23, 2001
- Alliance Semiconductor Corporation
- Perumal Ratnam
- H01 - BASIC ELECTRIC ELEMENTS

Perumal Ratnam

Person

Patents Grantslast 30 patents

Barrier modulated cell structures with intrinsic vertical bit line...

Multi-gate vertical field effect transistor with channel strips lat...

Memory hole bit line structures

Three-dimensional memory device with vertical semiconductor bit lin...

Resistive three-dimensional memory device with heterostructure semi...

Reversible resistivity memory with crystalline silicon bit line

Low forming voltage non-volatile storage device

Intrinsic vertical bit line architecture

Controlling adjustable resistance bit lines connected to word line...

Setting channel voltages of adjustable resistance bit line structur...

Side wall bit line structures

Vertical memory cells and methods of operation

Low forming voltage non-volatile storage device

Shared-gate vertical-TFT for vertical bit line array

Vertical memory cells and methods, architectures and devices for th...

Photodiode for multiple wavelength operation

Techniques for erasing an erasable programmable read only memory (E...

Flash EPROM memory cell having increased capacitive coupling and me...

Semiconductor device having reduced source leakage during source erase

Technique to improve the source leakage of flash EPROM cells during...

Flash EPROM memory cell having increased capacitive coupling

Method of and apparatus for increasing load resistance within an SR...

Making walled emitter bipolar transistor with reduced base narrowing

Patents Applicationslast 30 patents

BARRIER MODULATED CELL STRUCTURES WITH INTRINSIC VERTICAL BIT LINE...

MULTI-GATE VERTICAL FIELD EFFECT TRANSISTOR WITH CHANNEL STRIPS LAT...

THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL SEMICONDUCTOR BIT LIN...

LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE

REDUCING DISTURB WITH ADJUSTABLE RESISTANCE BIT LINE STRUCTURES

INTRINSIC VERTICAL BIT LINE ARCHITECTURE

OPERATION MODES FOR ADJUSTABLE RESISTANCE BIT LINE STRUCTURES

CONTROLLING ADJUSTABLE RESISTANCE BIT LINES CONNECTED TO WORD LINE...

SIDE WALL BIT LINE STRUCTURES

MEMORY HOLE BIT LINE STRUCTURES

SETTING CHANNEL VOLTAGES USING A DUMMY WORD LINE

SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY

LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE

SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR...

SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR...

PHOTODIODE FOR MULTIPLE WAVELENGTH OPERATION

Photodiodes with anti-reflection coating

Flash eprom memory cell having increased capacitive coupling and me...