Pete Hudson

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Escondido, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Chip scale packaging on CTE matched printed wiring boards
- Patent number 6,757,968
- Issue date Jul 6, 2004
- The Boeing Company
- Ching P. Lo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip scale packaging on CTE matched printed wiring boards
- Patent number 6,560,108
- Issue date May 6, 2003
- Hughes Electronics Corporation
- Ching P. Lo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip scale package
- Patent number 6,109,369
- Issue date Aug 29, 2000
- Delphi Technologies, Inc.
- William Robert Crumly
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layer to layer interconnect
- Patent number 6,007,669
- Issue date Dec 28, 1999
- Packard Hughes Interconnect Company
- William R. Crumly
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Chip scale packaging on CTE matched printed wiring boards
- Publication number 20030011998
- Publication date Jan 16, 2003
- Hughes Electronics Corporation
- C. P. Lo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip scale packaging on cte matched printed wiring boards
- Publication number 20010046120
- Publication date Nov 29, 2001
- C. P. Lo
- H01 - BASIC ELECTRIC ELEMENTS