Peter A. Beerel

Person

Westminister, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Timing violation resilient asynchronous template
- Patent number 9,875,327
- Issue date Jan 23, 2018
- University of Southern California
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Timing violation resilient asynchronous template
- Patent number 9,558,309
- Issue date Jan 31, 2017
- University of Southern California
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Static timing analysis of template-based asynchronous circuits
- Patent number 8,972,915
- Issue date Mar 3, 2015
- University of Southern California
- Mallika Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level domino, bundled data, and mixed templates
- Patent number 8,495,543
- Issue date Jul 23, 2013
- University of Southern California
- Georgios Dimou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clustering and fanout optimizations of asynchronous circuits
- Patent number 8,448,105
- Issue date May 21, 2013
- University of Southern California
- Georgios Dimou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power aware asynchronous circuits
- Patent number 8,086,975
- Issue date Dec 27, 2011
- University of Southern California
- Ken Shiring
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesis of multi-level domino asynchronous pipelines
- Patent number 8,051,396
- Issue date Nov 1, 2011
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesis of multi-level domino asynchronous pipelines
- Patent number 7,584,449
- Issue date Sep 1, 2009
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced-latency soft-in/soft-out module
- Patent number 7,197,691
- Issue date Mar 27, 2007
- University of Southern California
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimization of cell subtypes in a hierarchical design flow
- Patent number 6,854,096
- Issue date Feb 8, 2005
- Fulcrum Microsystems, Inc.
- Frederik Eaton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for facilitating physical synthesis of an int...
- Patent number 6,785,875
- Issue date Aug 31, 2004
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential decoder for decoding of convolutional codes
- Patent number 6,690,752
- Issue date Feb 10, 2004
- University of Southern California
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE
- Publication number 20160154905
- Publication date Jun 2, 2016
- University of Southern California
- Peter A. Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE
- Publication number 20150326210
- Publication date Nov 12, 2015
- University of Southern California
- Peter A. Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL DOMINO, BUNDLED DATA, AND MIXED TEMPLATES
- Publication number 20110029941
- Publication date Feb 3, 2011
- University of Southern California
- Georgios Dimou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS
- Publication number 20090288059
- Publication date Nov 19, 2009
- University of Southern California
- Georgios Dimou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER AWARE ASYNCHRONOUS CIRCUITS
- Publication number 20090288058
- Publication date Nov 19, 2009
- University of Southern California
- Ken Shiring
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES
- Publication number 20090217232
- Publication date Aug 27, 2009
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC TIMING ANALYSIS OF TEMPLATE-BASED ASYNCHRONOUS CIRCUITS
- Publication number 20090210841
- Publication date Aug 20, 2009
- University of Southern California
- Mallika Prakash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic synthesis of multi-level domino asynchronous pipelines
- Publication number 20060120189
- Publication date Jun 8, 2006
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reduced-latency soft-in/soft-out module
- Publication number 20040237025
- Publication date Nov 25, 2004
- University of Southern California
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Optimization of cell subtypes in a hierarchical design flow
- Publication number 20040103377
- Publication date May 27, 2004
- Fulcrum Microsystems, Inc.
- Frederik Eaton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for facilitating physical synthesis of an int...
- Publication number 20040034844
- Publication date Feb 19, 2004
- Fulcrum Microsystems, Inc.
- Peter Beerel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sequential decoder for decoding of convolutional codes
- Publication number 20020097817
- Publication date Jul 25, 2002
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reduced-latency soft-in/soft-out module
- Publication number 20020021770
- Publication date Feb 21, 2002
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY

Peter A. Beerel

Person

Patents Grantslast 30 patents

Timing violation resilient asynchronous template

Timing violation resilient asynchronous template

Static timing analysis of template-based asynchronous circuits

Multi-level domino, bundled data, and mixed templates

Clustering and fanout optimizations of asynchronous circuits

Power aware asynchronous circuits

Logic synthesis of multi-level domino asynchronous pipelines

Logic synthesis of multi-level domino asynchronous pipelines

Reduced-latency soft-in/soft-out module

Optimization of cell subtypes in a hierarchical design flow

Methods and apparatus for facilitating physical synthesis of an int...

Sequential decoder for decoding of convolutional codes

Patents Applicationslast 30 patents

TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE

TIMING VIOLATION RESILIENT ASYNCHRONOUS TEMPLATE

MULTI-LEVEL DOMINO, BUNDLED DATA, AND MIXED TEMPLATES

CLUSTERING AND FANOUT OPTIMIZATIONS OF ASYNCHRONOUS CIRCUITS

POWER AWARE ASYNCHRONOUS CIRCUITS

LOGIC SYNTHESIS OF MULTI-LEVEL DOMINO ASYNCHRONOUS PIPELINES

STATIC TIMING ANALYSIS OF TEMPLATE-BASED ASYNCHRONOUS CIRCUITS

Logic synthesis of multi-level domino asynchronous pipelines

Reduced-latency soft-in/soft-out module

Optimization of cell subtypes in a hierarchical design flow

Methods and apparatus for facilitating physical synthesis of an int...

Sequential decoder for decoding of convolutional codes

Reduced-latency soft-in/soft-out module