Peter B. HOLMQVIST

Person

Cary, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compression status bit cache and backing store
- Patent number 10,515,011
- Issue date Dec 24, 2019
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control mechanism for fine-tuned cache to backing-store synchroniza...
- Patent number 9,639,466
- Issue date May 2, 2017
- NVIDIA Corporation
- James Patrick Robertson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing memory traffic in DRAM ECC mode
- Patent number 9,110,809
- Issue date Aug 18, 2015
- NVIDIA Corporation
- Peter B. Holmqvist
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for evicting dirty data from a cache using a notificatio...
- Patent number 8,949,541
- Issue date Feb 3, 2015
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Padding buffer requests to avoid reads of invalid data
- Patent number 8,874,844
- Issue date Oct 28, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-class data cache policies
- Patent number 8,868,838
- Issue date Oct 21, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status caching
- Patent number 8,862,823
- Issue date Oct 14, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status bit cache and backing store
- Patent number 8,700,862
- Issue date Apr 15, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient line and page organization for compression status bit cac...
- Patent number 8,627,041
- Issue date Jan 7, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status bit cache with deterministic isochronous latency
- Patent number 8,595,437
- Issue date Nov 26, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing dynamically sized buffers within a cache
- Patent number 8,504,773
- Issue date Aug 6, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache and associated method with frame buffer managed dirty data pu...
- Patent number 8,464,001
- Issue date Jun 11, 2013
- Nvidia Corporation
- John H. Edmondson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Index-based zero-bandwidth clears
- Patent number 8,319,783
- Issue date Nov 27, 2012
- NVIDIA Corporation
- David Kirk McAllister
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Method and system for converting data formats using a shared cache...
- Patent number 8,271,734
- Issue date Sep 18, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for cleaning dirty data in an intermediate cache...
- Patent number 8,244,984
- Issue date Aug 14, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a data cache array as a DRAM load/store buffer
- Patent number 8,234,478
- Issue date Jul 31, 2012
- NVIDIA Corporation
- James Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L2 ECC implementation
- Patent number 8,156,404
- Issue date Apr 10, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache-based control of atomic operations in conjunction with an ext...
- Patent number 8,135,926
- Issue date Mar 13, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache occupancy policy
- Patent number 8,131,931
- Issue date Mar 6, 2012
- NVIDIA Corporation
- James Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing pipeline with latency bypass
- Patent number 8,125,489
- Issue date Feb 28, 2012
- NVIDIA Corporation
- Peter B. Holmqvist
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Cache-based control of atomic operations in conjunction with an ext...
- Patent number 8,108,610
- Issue date Jan 31, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L2 ECC implementation
- Patent number 8,099,650
- Issue date Jan 17, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method and frame buffer logic for evicting dirty data from...
- Patent number 8,060,700
- Issue date Nov 15, 2011
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for reducing memory bandwidth requirements in an...
- Patent number 7,868,901
- Issue date Jan 11, 2011
- NVIDIA Corporation
- John H. Edmondson
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Asynchronous reorder buffer
- Patent number 7,791,611
- Issue date Sep 7, 2010
- NVIDIA Corporation
- Peter Holmqvist
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to ensure consistency of depth values computed...
- Patent number 7,659,893
- Issue date Feb 9, 2010
- NVIDIA Corporation
- Stuart F. Oberman
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
REDUCING MEMORY TRAFFIC IN DRAM ECC MODE
- Publication number 20150012705
- Publication date Jan 8, 2015
- NVIDIA Corporation
- Peter B. HOLMQVIST
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION STATUS BIT CACHE AND BACKING STORE
- Publication number 20140237189
- Publication date Aug 21, 2014
- NVIDIA Corporation
- David B. GLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL MECHANISM FOR FINE-TUNED CACHE TO BACKING-STORE SYNCHRONIZA...
- Publication number 20140122809
- Publication date May 1, 2014
- NVIDIA Corporation
- James Patrick ROBERTSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Class Dependent Clean and Dirty Policy
- Publication number 20130124802
- Publication date May 16, 2013
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CAC...
- Publication number 20110087840
- Publication date Apr 14, 2011
- David B. GLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compression Status Bit Cache And Backing Store
- Publication number 20100138614
- Publication date Jun 3, 2010
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING

Peter B. HOLMQVIST

Person

Patents Grantslast 30 patents

Compression status bit cache and backing store

Control mechanism for fine-tuned cache to backing-store synchroniza...

Reducing memory traffic in DRAM ECC mode

Techniques for evicting dirty data from a cache using a notificatio...

Padding buffer requests to avoid reads of invalid data

Multi-class data cache policies

Compression status caching

Compression status bit cache and backing store

Efficient line and page organization for compression status bit cac...

Compression status bit cache with deterministic isochronous latency

Storing dynamically sized buffers within a cache

Cache and associated method with frame buffer managed dirty data pu...

Index-based zero-bandwidth clears

Method and system for converting data formats using a shared cache...

System and method for cleaning dirty data in an intermediate cache...

Using a data cache array as a DRAM load/store buffer

L2 ECC implementation

Cache-based control of atomic operations in conjunction with an ext...

Configurable cache occupancy policy

Processing pipeline with latency bypass

Cache-based control of atomic operations in conjunction with an ext...

L2 ECC implementation

System, method and frame buffer logic for evicting dirty data from...

Method and system for reducing memory bandwidth requirements in an...

Asynchronous reorder buffer

Method and apparatus to ensure consistency of depth values computed...

Patents Applicationslast 30 patents

REDUCING MEMORY TRAFFIC IN DRAM ECC MODE

COMPRESSION STATUS BIT CACHE AND BACKING STORE

CONTROL MECHANISM FOR FINE-TUNED CACHE TO BACKING-STORE SYNCHRONIZA...

Class Dependent Clean and Dirty Policy

EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CAC...

Compression Status Bit Cache And Backing Store