Peter D. Vogt

Person

Boulder, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Extended platform with additional memory module slots per CPU socke...
- Patent number 10,599,592
- Issue date Mar 24, 2020
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,592,445
- Issue date Mar 17, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Remote memory operations
- Patent number 10,509,738
- Issue date Dec 17, 2019
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read delivery for memory subsystem with narrow bandwidth repeater c...
- Patent number 10,339,072
- Issue date Jul 2, 2019
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for implementing die recovery in...
- Patent number 10,249,597
- Issue date Apr 2, 2019
- Intel Corporation
- Lakshminarayana Pappu
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended platform with additional memory module slots per CPU socket
- Patent number 10,242,717
- Issue date Mar 26, 2019
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended platform with additional memory module slots per CPU socke...
- Patent number 10,216,657
- Issue date Feb 26, 2019
- Intel Corporation
- Bruce Querbach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,146,711
- Issue date Dec 4, 2018
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended application of error checking and correction code in memory
- Patent number 10,120,749
- Issue date Nov 6, 2018
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Embedded ECC address mapping
- Patent number 10,031,802
- Issue date Jul 24, 2018
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous memory die stacking for energy efficient computing
- Patent number 9,841,920
- Issue date Dec 12, 2017
- Intel Corporation
- Pete D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended platform with additional memory module slots per CPU socket
- Patent number 9,818,457
- Issue date Nov 14, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 9,768,148
- Issue date Sep 19, 2017
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device responding to device commands for operational controls
- Patent number 9,652,170
- Issue date May 16, 2017
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory allowing variance in device interconnects
- Patent number 9,627,357
- Issue date Apr 18, 2017
- Intel Corporation
- Kenneth Shoemaker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory channel having deskew separate from redrive
- Patent number 9,335,373
- Issue date May 10, 2016
- Intel Corporation
- Pete D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method to reduce power delivery noise for partial writes
- Patent number 9,240,250
- Issue date Jan 19, 2016
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device responding to device commands for operational controls
- Patent number 9,223,718
- Issue date Dec 29, 2015
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 8,971,087
- Issue date Mar 3, 2015
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for improving bandwidth in stacked memory devices
- Patent number 8,964,443
- Issue date Feb 24, 2015
- Intel Corporation
- Peter D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, system and apparatus for evaluation of input/output buffer...
- Patent number 8,843,794
- Issue date Sep 23, 2014
- Intel Corporation
- Christopher J. Nelson
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory channel having deskew separate from redrive
- Patent number 8,756,450
- Issue date Jun 17, 2014
- Intel Corporation
- Pete D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,510,612
- Issue date Aug 13, 2013
- Intel Corporation
- Pete D. Vogt
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,489,944
- Issue date Jul 16, 2013
- Intel Corporation
- Warren Morrow
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,286,039
- Issue date Oct 9, 2012
- Intel Corporation
- Pete D. Vogt
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory channel having deskew separate from redrive
- Patent number 8,171,331
- Issue date May 1, 2012
- Intel Corporation
- Pete D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Disabling outbound drivers for a last memory buffer on a memory cha...
- Patent number 8,135,999
- Issue date Mar 13, 2012
- Intel Corporation
- Warren Morrow
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Training pattern for a biased clock recovery tracking loop
- Patent number 8,098,783
- Issue date Jan 17, 2012
- Intel Corporation
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Memory channel with bit lane fail-over
- Patent number 8,020,056
- Issue date Sep 13, 2011
- Intel Corporation
- Pete D. Vogt
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Combined command and data code
- Patent number 7,827,462
- Issue date Nov 2, 2010
- Intel Corporation
- Pete D. Vogt
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20190304953
- Publication date Oct 3, 2019
- Intel Corporation
- Pete D. VOGT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...
- Publication number 20190258594
- Publication date Aug 22, 2019
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...
- Publication number 20190213148
- Publication date Jul 11, 2019
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HETEROGENEOUS MEMORY DIE STACKING FOR ENERGY EFFICIENT COMPUTING
- Publication number 20180210674
- Publication date Jul 26, 2018
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET
- Publication number 20180130505
- Publication date May 10, 2018
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S
- Publication number 20180122779
- Publication date May 3, 2018
- Pete D. VOGT
- G11 - INFORMATION STORAGE
Information Patent Application
EXTENDED APPLICATION OF ERROR CHECKING AND CORRECTION CODE IN MEMORY
- Publication number 20180095821
- Publication date Apr 5, 2018
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING DIE RECOVERY IN...
- Publication number 20180096971
- Publication date Apr 5, 2018
- Intel Corporation
- LAKSHMINARAYANA PAPPU
- G11 - INFORMATION STORAGE
Information Patent Application
EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...
- Publication number 20180095909
- Publication date Apr 5, 2018
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMOTE MEMORY OPERATIONS
- Publication number 20180004687
- Publication date Jan 4, 2018
- Intel Corporation
- Francesc GUIM BERNAT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER C...
- Publication number 20170285941
- Publication date Oct 5, 2017
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER...
- Publication number 20170289850
- Publication date Oct 5, 2017
- Intel Corporation
- Bill NALE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL
- Publication number 20170285992
- Publication date Oct 5, 2017
- Intel Corporation
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques to Access or Operate a Dual In-Line Memory Module via Mu...
- Publication number 20170199830
- Publication date Jul 13, 2017
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE RESPONDING TO DEVICE COMMANDS FOR OPERATIONAL CONTROLS
- Publication number 20160170676
- Publication date Jun 16, 2016
- Intel Corporation
- Pete Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20150108660
- Publication date Apr 23, 2015
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BROADCAST COMMAND
- Publication number 20150089127
- Publication date Mar 26, 2015
- KULJIT S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CHANNEL HAVING DESKEW SEPARATE FROM REDRIVE
- Publication number 20150046760
- Publication date Feb 12, 2015
- Pete D. Vogt
- G01 - MEASURING TESTING
Information Patent Application
EMBEDDED ECC ADDRESS MAPPING
- Publication number 20150006993
- Publication date Jan 1, 2015
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO REDUCE POWER DELIVERY NOISE FOR PARTIAL WRITES
- Publication number 20140372815
- Publication date Dec 18, 2014
- KULJIT S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR IMPROVING BANDWIDTH IN STACKED MEMORY DEVICES
- Publication number 20140362630
- Publication date Dec 11, 2014
- Peter D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Application
HETEROGENEOUS MEMORY DIE STACKING FOR ENERGY EFFICIENT COMPUTING
- Publication number 20140310490
- Publication date Oct 16, 2014
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER...
- Publication number 20140089752
- Publication date Mar 27, 2014
- Christopher J. Nelson
- G01 - MEASURING TESTING
Information Patent Application
MEMORY DEVICE RESPONDING TO DEVICE COMMANDS FOR OPERATIONAL CONTROLS
- Publication number 20130297863
- Publication date Nov 7, 2013
- Pete Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY ALLOWING VARIANCE IN DEVICE INTERCONNECTS
- Publication number 20130292840
- Publication date Nov 7, 2013
- Kenneth Shoemaker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20130272049
- Publication date Oct 17, 2013
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Application
DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...
- Publication number 20130097371
- Publication date Apr 18, 2013
- Warren Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...
- Publication number 20120331356
- Publication date Dec 27, 2012
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHANNEL HAVING DESKEW SEPARATE FROM REDRIVE
- Publication number 20120188832
- Publication date Jul 26, 2012
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...
- Publication number 20120102256
- Publication date Apr 26, 2012
- Pete D. Vogt
- G06 - COMPUTING CALCULATING COUNTING

Peter D. Vogt

Person

Patents Grantslast 30 patents

Extended platform with additional memory module slots per CPU socke...

Techniques to access or operate a dual in-line memory module via mu...

Remote memory operations

Read delivery for memory subsystem with narrow bandwidth repeater c...

Systems, methods, and apparatuses for implementing die recovery in...

Extended platform with additional memory module slots per CPU socket

Extended platform with additional memory module slots per CPU socke...

Techniques to access or operate a dual in-line memory module via mu...

Extended application of error checking and correction code in memory

Embedded ECC address mapping

Heterogeneous memory die stacking for energy efficient computing

Extended platform with additional memory module slots per CPU socket

Stacked memory with interface providing offset interconnects

Memory device responding to device commands for operational controls

Stacked memory allowing variance in device interconnects

Memory channel having deskew separate from redrive

Apparatus and method to reduce power delivery noise for partial writes

Memory device responding to device commands for operational controls

Stacked memory with interface providing offset interconnects

Method for improving bandwidth in stacked memory devices

Method, system and apparatus for evaluation of input/output buffer...

Memory channel having deskew separate from redrive

Disabling outbound drivers for a last memory buffer on a memory cha...

Disabling outbound drivers for a last memory buffer on a memory cha...

Disabling outbound drivers for a last memory buffer on a memory cha...

Memory channel having deskew separate from redrive

Disabling outbound drivers for a last memory buffer on a memory cha...

Training pattern for a biased clock recovery tracking loop

Memory channel with bit lane fail-over

Combined command and data code

Patents Applicationslast 30 patents

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...

TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...

HETEROGENEOUS MEMORY DIE STACKING FOR ENERGY EFFICIENT COMPUTING

EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKET

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S

EXTENDED APPLICATION OF ERROR CHECKING AND CORRECTION CODE IN MEMORY

SYSTEMS, METHODS, AND APPARATUSES FOR IMPLEMENTING DIE RECOVERY IN...

EXTENDED PLATFORM WITH ADDITIONAL MEMORY MODULE SLOTS PER CPU SOCKE...

REMOTE MEMORY OPERATIONS

READ DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER C...

WRITE DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER...

MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL

Techniques to Access or Operate a Dual In-Line Memory Module via Mu...

MEMORY DEVICE RESPONDING TO DEVICE COMMANDS FOR OPERATIONAL CONTROLS

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

MEMORY BROADCAST COMMAND

MEMORY CHANNEL HAVING DESKEW SEPARATE FROM REDRIVE

EMBEDDED ECC ADDRESS MAPPING

APPARATUS AND METHOD TO REDUCE POWER DELIVERY NOISE FOR PARTIAL WRITES

METHOD FOR IMPROVING BANDWIDTH IN STACKED MEMORY DEVICES

HETEROGENEOUS MEMORY DIE STACKING FOR ENERGY EFFICIENT COMPUTING

METHOD, SYSTEM AND APPARATUS FOR EVALUATION OF INPUT/OUTPUT BUFFER...

MEMORY DEVICE RESPONDING TO DEVICE COMMANDS FOR OPERATIONAL CONTROLS

STACKED MEMORY ALLOWING VARIANCE IN DEVICE INTERCONNECTS

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...

DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...

MEMORY CHANNEL HAVING DESKEW SEPARATE FROM REDRIVE

DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHA...