Peter Feeley

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Managing error-handling flows in memory devices
- Patent number 12,229,000
- Issue date Feb 18, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with dynamic cache management
- Patent number 12,216,573
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices and systems including static and dynamic caches, and...
- Patent number 12,131,020
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer allocation for reducing block transit penalty
- Patent number 12,079,517
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage calibration scans to reduce memory device overhead
- Patent number 12,057,185
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory block programming using defectivity information
- Patent number 12,051,479
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple-pass programming of memory cells using temporary parity ge...
- Patent number 12,001,721
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage bin calibration based on a voltage distribution reference v...
- Patent number 11,966,616
- Issue date Apr 23, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing voltage bin selection for blocks of a memory device
- Patent number 11,928,347
- Issue date Mar 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing fault tolerant page stripes on low density memory systems
- Patent number 11,899,966
- Issue date Feb 13, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block family-based error avoidance for memory devices
- Patent number 11,886,726
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Michael Sheperek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjusting pass-through voltage based on threshold voltage shift
- Patent number 11,869,605
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Providing recovered data to a new memory cell at a memory sub-syste...
- Patent number 11,868,639
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Sampath K. Ratnam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with dynamic cache management
- Patent number 11,853,205
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable trim settings on a memory device
- Patent number 11,854,634
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable trim settings on a memory device
- Patent number 11,853,207
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Relocating data to low latency memory
- Patent number 11,836,392
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing error-handling flows in memory devices
- Patent number 11,837,307
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Trim setting determination on a memory device
- Patent number 11,836,078
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Garbage collection candidate selection using block overwrite rate
- Patent number 11,829,290
- Issue date Nov 28, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining voltage offsets for memory read operations
- Patent number 11,823,722
- Issue date Nov 21, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage bin calibration based on a temporary voltage shift offset
- Patent number 11,823,748
- Issue date Nov 21, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Trim setting determination for a memory device
- Patent number 11,817,164
- Issue date Nov 14, 2023
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant array of independent NAND for a three-dimensional memory...
- Patent number 11,797,383
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- Jung Sheng Hoei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache media management
- Patent number 11,797,441
- Issue date Oct 24, 2023
- Micron Technology, Inc.
- Ashutosh Malshe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-on-time based data relocation
- Patent number 11,789,862
- Issue date Oct 17, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing a media management operation based on a sequence identif...
- Patent number 11,782,847
- Issue date Oct 10, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Periodic flush in memory component that is using greedy garbage col...
- Patent number 11,755,472
- Issue date Sep 12, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Grouping blocks based on power cycle and power on time
- Patent number 11,748,013
- Issue date Sep 5, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing critical data at a memory system
- Patent number 11,726,874
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Vamsi Rayaprolu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICES AND SYSTEMS INCLUDING HYBRID CACHE, AND RELATED METHODS
- Publication number 20250013364
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
- Publication number 20240393980
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
- Publication number 20240347128
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...
- Publication number 20240302999
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE V...
- Publication number 20240231676
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRIM SETTING DETERMINATION ON A MEMORY DEVICE
- Publication number 20240211395
- Publication date Jun 27, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE
- Publication number 20240203516
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRIM SETTING DETERMINATION FOR A MEMORY DEVICE
- Publication number 20240161846
- Publication date May 16, 2024
- Micron Technology, Inc.
- Aswin Thiruvengadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT
- Publication number 20240126690
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES
- Publication number 20240111445
- Publication date Apr 4, 2024
- Micron Technology, Inc.
- Michael Sheperek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING RECOVERED DATA TO A NEW MEMORY CELL AT A MEMORY SUB-SYSTE...
- Publication number 20240103749
- Publication date Mar 28, 2024
- Micron Technology, Inc.
- Sampath K. Ratnam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...
- Publication number 20240045616
- Publication date Feb 8, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
- Publication number 20240028259
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
- Publication number 20240029815
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES
- Publication number 20230325273
- Publication date Oct 12, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING VOLTAGE OFFSETS FOR MEMORY READ OPERATIONS
- Publication number 20230282293
- Publication date Sep 7, 2023
- Micron Technology, Inc.
- Kishore Kumar MUCHHERLA
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING VOLTAGE BIN SELECTION FOR BLOCKS OF A MEMORY DEVICE
- Publication number 20230205438
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE V...
- Publication number 20230205447
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESEQUENCING DATA PROGRAMMED TO MULTIPLE LEVEL MEMORY CELLS AT A ME...
- Publication number 20230195350
- Publication date Jun 22, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT
- Publication number 20230195615
- Publication date Jun 22, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE CALIBRATION SCANS TO REDUCE MEMORY DEVICE OVERHEAD
- Publication number 20230122275
- Publication date Apr 20, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A COMMON POOL OF BLOCKS FOR USER DATA AND A SYSTEM DATA STRUC...
- Publication number 20230088790
- Publication date Mar 23, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES
- Publication number 20230046724
- Publication date Feb 16, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
GROUPING BLOCKS BASED ON POWER CYCLE AND POWER ON TIME
- Publication number 20230017591
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING A MEDIA MANAGEMENT OPERATION BASED ON A SEQUENCE IDENTIF...
- Publication number 20220414021
- Publication date Dec 29, 2022
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTING PASS-THROUGH VOLTAGE BASED ON THRESHOLD VOLTAGE SHIFT
- Publication number 20220392554
- Publication date Dec 8, 2022
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
VOLTAGE BIN CALIBRATION BASED ON A TEMPORARY VOTLAGE SHIFT OFFSET
- Publication number 20220392547
- Publication date Dec 8, 2022
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
VOLTAGE BIN SELECTION FOR BLOCKS OF A MEMORY DEVICE AFTER POWER UP...
- Publication number 20220383955
- Publication date Dec 1, 2022
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
IMPLEMENTING FAULT TOLERANT PAGE STRIPES ON LOW DENSITY MEMORY SYSTEMS
- Publication number 20220357873
- Publication date Nov 10, 2022
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MITIGATING A VOLTAGE CONDITION OF A MEMORY CELL IN A MEMORY SUB-SYSTEM
- Publication number 20220351786
- Publication date Nov 3, 2022
- Micron Technology, Inc.
- Vamsi Pavan Rayaprolu
- G06 - COMPUTING CALCULATING COUNTING

Peter Feeley

Person

Patents Grantslast 30 patents

Managing error-handling flows in memory devices

Memory device with dynamic cache management

Memory devices and systems including static and dynamic caches, and...

Buffer allocation for reducing block transit penalty

Voltage calibration scans to reduce memory device overhead

Memory block programming using defectivity information

Multiple-pass programming of memory cells using temporary parity ge...

Voltage bin calibration based on a voltage distribution reference v...

Managing voltage bin selection for blocks of a memory device

Implementing fault tolerant page stripes on low density memory systems

Block family-based error avoidance for memory devices

Adjusting pass-through voltage based on threshold voltage shift

Providing recovered data to a new memory cell at a memory sub-syste...

Memory device with dynamic cache management

Selectable trim settings on a memory device

Configurable trim settings on a memory device

Relocating data to low latency memory

Managing error-handling flows in memory devices

Trim setting determination on a memory device

Garbage collection candidate selection using block overwrite rate

Determining voltage offsets for memory read operations

Voltage bin calibration based on a temporary voltage shift offset

Trim setting determination for a memory device

Redundant array of independent NAND for a three-dimensional memory...

Cache media management

Power-on-time based data relocation

Performing a media management operation based on a sequence identif...

Periodic flush in memory component that is using greedy garbage col...

Grouping blocks based on power cycle and power on time

Storing critical data at a memory system

Patents Applicationslast 30 patents

MEMORY DEVICES AND SYSTEMS INCLUDING HYBRID CACHE, AND RELATED METHODS

BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY

MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION

MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...

VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE V...

TRIM SETTING DETERMINATION ON A MEMORY DEVICE

SELECTABLE TRIM SETTINGS ON A MEMORY DEVICE

TRIM SETTING DETERMINATION FOR A MEMORY DEVICE

MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT

BLOCK FAMILY-BASED ERROR AVOIDANCE FOR MEMORY DEVICES

PROVIDING RECOVERED DATA TO A NEW MEMORY CELL AT A MEMORY SUB-SYSTE...

MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...

BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY

MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION

MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES

DETERMINING VOLTAGE OFFSETS FOR MEMORY READ OPERATIONS

MANAGING VOLTAGE BIN SELECTION FOR BLOCKS OF A MEMORY DEVICE

VOLTAGE BIN CALIBRATION BASED ON A VOLTAGE DISTRIBUTION REFERENCE V...

RESEQUENCING DATA PROGRAMMED TO MULTIPLE LEVEL MEMORY CELLS AT A ME...

MEMORY DEVICE WITH DYNAMIC CACHE MANAGEMENT

VOLTAGE CALIBRATION SCANS TO REDUCE MEMORY DEVICE OVERHEAD

USING A COMMON POOL OF BLOCKS FOR USER DATA AND A SYSTEM DATA STRUC...

MANAGING ERROR-HANDLING FLOWS IN MEMORY DEVICES

GROUPING BLOCKS BASED ON POWER CYCLE AND POWER ON TIME

PERFORMING A MEDIA MANAGEMENT OPERATION BASED ON A SEQUENCE IDENTIF...

ADJUSTING PASS-THROUGH VOLTAGE BASED ON THRESHOLD VOLTAGE SHIFT

VOLTAGE BIN CALIBRATION BASED ON A TEMPORARY VOTLAGE SHIFT OFFSET

VOLTAGE BIN SELECTION FOR BLOCKS OF A MEMORY DEVICE AFTER POWER UP...

IMPLEMENTING FAULT TOLERANT PAGE STRIPES ON LOW DENSITY MEMORY SYSTEMS

MITIGATING A VOLTAGE CONDITION OF A MEMORY CELL IN A MEMORY SUB-SYSTEM