Peter G. Sassone

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method of VLIW instruction processing using reduced-widt...
- Patent number 11,663,011
- Issue date May 30, 2023
- QUALCOMM Incorporated
- Peter Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of VLIW instruction processing using reduced-widt...
- Patent number 10,719,325
- Issue date Jul 21, 2020
- QUALCOMM Incorporated
- Peter Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid write-through/write-back cache policy managers, and related...
- Patent number 10,025,711
- Issue date Jul 17, 2018
- QUALCOMM Incorporated
- Peter G. Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple clustered very long instruction word processing core
- Patent number 9,715,392
- Issue date Jul 25, 2017
- QUALCOMM Incorporated
- Suresh Kumar Venkumahanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency-based power mode units for controlling power modes of proce...
- Patent number 9,552,033
- Issue date Jan 24, 2017
- QUALCOMM Incorporated
- Suresh Kumar Venkumahanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data cache way prediction
- Patent number 9,367,468
- Issue date Jun 14, 2016
- QUALCOMM Incorporated
- Peter G. Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction cache having a multi-bit way prediction mask
- Patent number 9,304,932
- Issue date Apr 5, 2016
- QUALCOMM Incorporated
- Peter G. Sassone
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Instruction boundary prediction for variable length instruction set
- Patent number 9,223,714
- Issue date Dec 29, 2015
- Intel Corporation
- Mauricio Breternitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient Bloom filter
- Patent number 7,620,781
- Issue date Nov 17, 2009
- Intel Corporation
- Mauricio Breternitz, Jr.
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDT...
- Publication number 20200364051
- Publication date Nov 19, 2020
- Qualcomm Incorporated
- Peter SASSONE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDT...
- Publication number 20190138311
- Publication date May 9, 2019
- QUALCOMM Incorporated
- Peter SASSONE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE CLUSTERED VERY LONG INSTRUCTION WORD PROCESSING CORE
- Publication number 20160062770
- Publication date Mar 3, 2016
- QUALCOMM Incorporated
- Suresh Kumar Venkumahanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATENCY-BASED POWER MODE UNITS FOR CONTROLLING POWER MODES OF PROCE...
- Publication number 20150301573
- Publication date Oct 22, 2015
- QUALCOMM Incorporated
- Suresh Kumar Venkumahanti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION BOUNDARY PREDICTION FOR VARIABLE LENGTH INSTRUCTION SET
- Publication number 20140281246
- Publication date Sep 18, 2014
- Mauricio Breternitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA CACHE WAY PREDICTION
- Publication number 20140201449
- Publication date Jul 17, 2014
- QUALCOMM Incorporated
- Peter G. Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION CACHE HAVING A MULTI-BIT WAY PREDICTION MASK
- Publication number 20140181405
- Publication date Jun 26, 2014
- QUALCOMM Incorporated
- Peter G. Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hybrid Write-Through/Write-Back Cache Policy Managers, and Related...
- Publication number 20130185511
- Publication date Jul 18, 2013
- QUALCOMM Incorporated
- Peter G. Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Use of Loop and Addressing Mode Instruction Set Semantics to Direct...
- Publication number 20130185516
- Publication date Jul 18, 2013
- QUALCOMM Incorporated
- Peter G. Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Utilizing Negative Feedback from Unexpected Miss Addresses in a Har...
- Publication number 20130185515
- Publication date Jul 18, 2013
- QUALCOMM Incorporated
- Peter G. Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scheduling a direct dependent instruction
- Publication number 20080244224
- Publication date Oct 2, 2008
- Peter Sassone
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient bloom filter
- Publication number 20080147714
- Publication date Jun 19, 2008
- Mauricio Breternitz
- G06 - COMPUTING CALCULATING COUNTING

Peter G. Sassone

Person

Patents Grantslast 30 patents

System and method of VLIW instruction processing using reduced-widt...

System and method of VLIW instruction processing using reduced-widt...

Hybrid write-through/write-back cache policy managers, and related...

Multiple clustered very long instruction word processing core

Latency-based power mode units for controlling power modes of proce...

Data cache way prediction

Instruction cache having a multi-bit way prediction mask

Instruction boundary prediction for variable length instruction set

Efficient Bloom filter

Patents Applicationslast 30 patents

SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDT...

SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDT...

MULTIPLE CLUSTERED VERY LONG INSTRUCTION WORD PROCESSING CORE

LATENCY-BASED POWER MODE UNITS FOR CONTROLLING POWER MODES OF PROCE...

INSTRUCTION BOUNDARY PREDICTION FOR VARIABLE LENGTH INSTRUCTION SET

DATA CACHE WAY PREDICTION

INSTRUCTION CACHE HAVING A MULTI-BIT WAY PREDICTION MASK

Hybrid Write-Through/Write-Back Cache Policy Managers, and Related...

Use of Loop and Addressing Mode Instruction Set Semantics to Direct...

Utilizing Negative Feedback from Unexpected Miss Addresses in a Har...

Scheduling a direct dependent instruction

Efficient bloom filter