Peter H. Alfke

Person

Los Altos Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Direct digital synthesis with reduced jitter
- Patent number 8,352,526
- Issue date Jan 8, 2013
- Xilinx, Inc.
- Peter H. Alfke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for measuring a time interval using a high-speed serial rec...
- Patent number 8,265,902
- Issue date Sep 11, 2012
- Xilinx, Inc.
- Noel J. Brady
- G04 - HOROLOGY
Information Patent Grant
Glitch-suppressor circuits and methods
- Patent number 7,839,181
- Issue date Nov 23, 2010
- Xilinx, Inc.
- Peter H. Alfke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing noise on a supply voltage in an integrated circuit
- Patent number 7,755,381
- Issue date Jul 13, 2010
- Xilinx, Inc.
- Peter H. Alfke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Glitch-suppressor circuits and methods
- Patent number 7,667,500
- Issue date Feb 23, 2010
- Xilinx, Inc.
- Peter H. Alfke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit for and method of testing a memory device
- Patent number 7,574,635
- Issue date Aug 11, 2009
- Xilinx, Inc.
- Peter H. Alfke
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuits and methods of concatenating FIFOs
- Patent number 7,535,789
- Issue date May 19, 2009
- Xilinx, Inc.
- Thomas E. Fischaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct digital synthesis with low jitter
- Patent number 7,268,594
- Issue date Sep 11, 2007
- Xilinx, Inc.
- Peter H. Alfke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
First-in, first-out memory system with reduced cycle latency
- Patent number 7,254,677
- Issue date Aug 7, 2007
- Xilinx, Inc.
- Wayson J. Lowe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measuring pulse edge delay value relative to a clock using multiple...
- Patent number 7,227,387
- Issue date Jun 5, 2007
- Xilinx, Inc.
- Peter H. Alfke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
First-in, first-out buffer system in an integrated circuit
- Patent number 7,161,849
- Issue date Jan 9, 2007
- Xilinx, Inc.
- Wayson J. Lowe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large crossbar switch implemented in FPGA
- Patent number 7,057,413
- Issue date Jun 6, 2006
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuits and methods for analyzing timing characteristics of sequen...
- Patent number 7,020,862
- Issue date Mar 28, 2006
- Xilinx, Inc.
- Peter H. Alfke
- G01 - MEASURING TESTING
Information Patent Grant
Almost full, almost empty memory system
- Patent number 6,956,776
- Issue date Oct 18, 2005
- Xilinx, Inc.
- Wayson J. Lowe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for gray-coding counting
- Patent number 6,937,172
- Issue date Aug 30, 2005
- Xilinx, Inc.
- Wayson J. Lowe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
First-in, first-out buffer system in an integrated circuit
- Patent number 6,934,198
- Issue date Aug 23, 2005
- Xilinx, Inc.
- Wayson J. Lowe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controller arrangement for partial reconfiguration of a programmabl...
- Patent number 6,810,514
- Issue date Oct 26, 2004
- Xilinx, Inc.
- Peter H. Alfke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large crossbar switch implemented in FPGA
- Patent number 6,759,869
- Issue date Jul 6, 2004
- Xilinx, Inc.
- Steven P. Young
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuits and methods for analyzing timing characteristics of sequen...
- Patent number 6,734,703
- Issue date May 11, 2004
- Xilinx, Inc.
- Peter H. Alfke
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic device with partial battery backup
- Patent number 6,441,641
- Issue date Aug 27, 2002
- Xilinx, Inc.
- Raymond C. Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FIFO memory system and method with improved determination of full a...
- Patent number 6,434,642
- Issue date Aug 13, 2002
- Xilinx, Inc.
- Nicolas J. Camilleri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for suppressing input signal irregularities
- Patent number 6,407,612
- Issue date Jun 18, 2002
- Xilinx, Inc.
- Peter H. Alfke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FIFO memory system and method with improved generation of empty and...
- Patent number 6,389,490
- Issue date May 14, 2002
- Xilinx, Inc.
- Nicolas J. Camilleri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for discriminating against signal interference
- Patent number 6,353,341
- Issue date Mar 5, 2002
- Xilinx, Inc.
- Austin H. Lesea
- G01 - MEASURING TESTING
Information Patent Grant
FPGA control structure for self-reconfiguration
- Patent number 6,260,139
- Issue date Jul 10, 2001
- Xilinx, Inc.
- Peter H. Alfke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating circuit for reducing power consumption
- Patent number 6,204,695
- Issue date Mar 20, 2001
- Xilinx, Inc.
- Peter H. Alfke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User-controlled delay circuit for a programmable logic device
- Patent number 6,150,863
- Issue date Nov 21, 2000
- Xilinx, Inc.
- Robert O. Conn
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Oscillator for measuring on-chip delays
- Patent number 6,134,191
- Issue date Oct 17, 2000
- Xilinx, Inc.
- Peter H. Alfke
- G01 - MEASURING TESTING
Information Patent Grant
System for preventing radiation failures in programmable logic devices
- Patent number 6,104,211
- Issue date Aug 15, 2000
- Xilinx, Inc.
- Peter H. Alfke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Feedback apparatus for adjusting clock delay
- Patent number 6,002,282
- Issue date Dec 14, 1999
- Xilinx, Inc.
- Peter H. Alfke
- G06 - COMPUTING CALCULATING COUNTING

Peter H. Alfke

Person

Patents Grantslast 30 patents

Direct digital synthesis with reduced jitter

Circuit for measuring a time interval using a high-speed serial rec...

Glitch-suppressor circuits and methods

Reducing noise on a supply voltage in an integrated circuit

Glitch-suppressor circuits and methods

Circuit for and method of testing a memory device

Circuits and methods of concatenating FIFOs

Direct digital synthesis with low jitter

First-in, first-out memory system with reduced cycle latency

Measuring pulse edge delay value relative to a clock using multiple...

First-in, first-out buffer system in an integrated circuit

Large crossbar switch implemented in FPGA

Circuits and methods for analyzing timing characteristics of sequen...

Almost full, almost empty memory system

Method and system for gray-coding counting

First-in, first-out buffer system in an integrated circuit

Controller arrangement for partial reconfiguration of a programmabl...

Large crossbar switch implemented in FPGA

Circuits and methods for analyzing timing characteristics of sequen...

Programmable logic device with partial battery backup

FIFO memory system and method with improved determination of full a...

Method and system for suppressing input signal irregularities

FIFO memory system and method with improved generation of empty and...

Method and apparatus for discriminating against signal interference

FPGA control structure for self-reconfiguration

Clock-gating circuit for reducing power consumption

User-controlled delay circuit for a programmable logic device

Oscillator for measuring on-chip delays

System for preventing radiation failures in programmable logic devices

Feedback apparatus for adjusting clock delay