Peter H. Voss

Person

Eindhoven, NL

People

Patents Grantslast 30 patents

Information Patent Grant
Pulse generator circuit arrangement
- Patent number 5,265,064
- Issue date Nov 23, 1993
- U.S. Philips Corp.
- Thomas J. Davies
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Addressable memory unit having an improved unit selection circuit
- Patent number 5,224,071
- Issue date Jun 29, 1993
- U.S. Philips Corp.
- Cormac O'Connell
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated output buffer logic circuit with a memory circuit
- Patent number 5,087,840
- Issue date Feb 11, 1992
- U.S. Philips Corp.
- Thomas J. Davies
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast static random access memory with high storage capacity
- Patent number 5,040,152
- Issue date Aug 13, 1991
- U.S. Philips Corp.
- Peter H. Voss
- G11 - INFORMATION STORAGE
Information Patent Grant
Matrix memory with redundancy and minimizes delay
- Patent number 5,033,024
- Issue date Jul 16, 1991
- U.S. Philips Corp.
- Cormac M. O'Connell
- G11 - INFORMATION STORAGE
Information Patent Grant
Static memory unit having a plurality of test modes, and computer e...
- Patent number 4,951,254
- Issue date Aug 21, 1990
- U.S. Philips Corporation
- Hans Ontrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangement for a dual bus line
- Patent number 4,931,667
- Issue date Jun 5, 1990
- U.S. Philips Corporation
- Leonardus C. M. G. Pfennings
- G11 - INFORMATION STORAGE
Information Patent Grant
Push-pull output circuit having three transistors
- Patent number 4,929,911
- Issue date May 29, 1990
- U.S. Philips Corp.
- Thomas J. Davies
- H03 - BASIC ELECTRONIC CIRCUITRY

Peter H. Voss

Person

Patents Grantslast 30 patents

Pulse generator circuit arrangement

Addressable memory unit having an improved unit selection circuit

Integrated output buffer logic circuit with a memory circuit

Fast static random access memory with high storage capacity

Matrix memory with redundancy and minimizes delay

Static memory unit having a plurality of test modes, and computer e...

Circuit arrangement for a dual bus line

Push-pull output circuit having three transistors