Peter H. Voss

Person

Watsonville, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Trapped-charge non-volatile memory with uniform multilevel programming
- Patent number 7,898,852
- Issue date Mar 1, 2011
- Cypress Semiconductor Corporation
- Sagy Levy
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power cache system and method
- Patent number 7,487,369
- Issue date Feb 3, 2009
- RMI Corporation
- Mayank Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory cell with a pre-programmed state
- Patent number 6,400,599
- Issue date Jun 4, 2002
- SandCraft, Inc.
- Peter H. Voss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to prevent latch-up in CMOS devices
- Patent number 6,359,316
- Issue date Mar 19, 2002
- Cypress Semiconductor Corp.
- Peter H. Voss
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital programmable delay element
- Patent number 6,255,879
- Issue date Jul 3, 2001
- Sand Craft, Inc.
- Peter H. Voss
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced line select decoder for a memory array
- Patent number 6,252,819
- Issue date Jun 26, 2001
- SandCraft, Inc.
- Peter H. Voss
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for operating a dual port memory cell
- Patent number 6,252,818
- Issue date Jun 26, 2001
- SandCraft, Inc.
- Peter Voss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated cache memory with system control logic and adaptation of...
- Patent number 6,131,140
- Issue date Oct 10, 2000
- Cypress Semiconductor Corp.
- Thurman J. Rodgers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory cell with a pre-programmed state
- Patent number 6,070,229
- Issue date May 30, 2000
- SandCraft, Inc.
- Peter H. Voss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM with ROM functionality
- Patent number 5,923,582
- Issue date Jul 13, 1999
- Cypress Semiconductor Corp.
- Peter H. Voss
- G11 - INFORMATION STORAGE
Information Patent Grant
Dummy cell for providing a reference voltage in a memory array
- Patent number 5,689,471
- Issue date Nov 18, 1997
- Cypress Semiconductor Corp.
- Peter H. Voss
- G11 - INFORMATION STORAGE
Information Patent Grant
Five transistor memory cell with shared power line
- Patent number 5,453,950
- Issue date Sep 26, 1995
- Cypress Semiconductor Corp.
- Peter H. Voss
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer with pseudo-ground hysteresis
- Patent number 5,386,153
- Issue date Jan 31, 1995
- Cypress Semiconductor Corporation
- Peter H. Voss
- H03 - BASIC ELECTRONIC CIRCUITRY

Peter H. Voss

Person

Patents Grantslast 30 patents

Trapped-charge non-volatile memory with uniform multilevel programming

Low-power cache system and method

Cache memory cell with a pre-programmed state

Method and apparatus to prevent latch-up in CMOS devices

Digital programmable delay element

Reduced line select decoder for a memory array

Apparatus and method for operating a dual port memory cell

Integrated cache memory with system control logic and adaptation of...

Cache memory cell with a pre-programmed state

SRAM with ROM functionality

Dummy cell for providing a reference voltage in a memory array

Five transistor memory cell with shared power line

Buffer with pseudo-ground hysteresis