Peter Hagemeyer

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Dresden, DE

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Patents Grantslast 30 patents

Information Patent Grant
Method for fabricating a layer arrangement, layer arrangement and m...
- Patent number 7,713,810
- Issue date May 11, 2010
- Infineon Technologies AG
- Peter Hagemeyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory cell with buried floating gate and method for operatin...
- Patent number 7,064,377
- Issue date Jun 20, 2006
- Infineon Technologies AG
- Peter Hagemeyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical transistor, memory arrangement and method for fabricating...
- Patent number 6,768,166
- Issue date Jul 27, 2004
- Infineon Technologies AG
- Peter Hagemeyer
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Layer arrangement and memory arrangement
- Publication number 20060008959
- Publication date Jan 12, 2006
- Peter Hagemeyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flash memory cell with buried floating gate and method for operatin...
- Publication number 20040228187
- Publication date Nov 18, 2004
- Peter Hagemeyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertical transistor, memory arrangement and method for fabricating...
- Publication number 20030015755
- Publication date Jan 23, 2003
- Peter Hagemeyer
- H01 - BASIC ELECTRIC ELEMENTS