Peter J. Meier

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low power parallelization to multiple output bus widths
- Patent number 9,767,062
- Issue date Sep 19, 2017
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Darrin C. Miller
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for high speed data parallelization for an N-phas...
- Patent number 8,902,091
- Issue date Dec 2, 2014
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Darrin C. Miller
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast lock clock-data recovery for phase steps
- Patent number 8,634,503
- Issue date Jan 21, 2014
- Avago Technologies General IP (Singapore) Pte Ltd
- Brian J. Misek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Internal loop-back architecture for parallel serializer/deserialize...
- Patent number 7,742,427
- Issue date Jun 22, 2010
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Michael Martin Farmer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for equalizing transition density in an integrate...
- Patent number 7,548,174
- Issue date Jun 16, 2009
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Michael Martin Farmer
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Integrated circuit design method for efficiently generating mask data
- Patent number 7,526,744
- Issue date Apr 28, 2009
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Robert J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay-locked loop and a method of testing a delay-locked loop
- Patent number 7,352,165
- Issue date Apr 1, 2008
- Avago Technologies General IP Pte. Ltd.
- Alvin Leng Sun Loke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay-locked loop and a method of testing a delay-locked loop
- Patent number 7,123,001
- Issue date Oct 17, 2006
- Avago Tehnologies General IP (Singapore) Pte. Ltd.
- Alvin Leng Sun Loke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay-locked loop and a method of testing a delay-locked loop
- Patent number 6,995,554
- Issue date Feb 7, 2006
- Agilent Technologies, Inc.
- Alvin Leng Sun Loke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit with alternately selectable state evaluation pro...
- Patent number 6,539,507
- Issue date Mar 25, 2003
- Agilent Technologies, Inc.
- Christopher M Juenemann
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for low cost set mapping
- Patent number 6,124,869
- Issue date Sep 26, 2000
- Agilent Technologies
- Brian C. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design system and method for generating a regula...
- Patent number 5,847,969
- Issue date Dec 8, 1998
- Hewlett-Packard Co.
- Brian C. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Symmetric edge true/complement buffer/inverter and method therefor
- Patent number 5,140,174
- Issue date Aug 18, 1992
- Hewlett-Packard Co.
- Peter Meier
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
LOW POWER PARALLELIZATION TO MULTIPLE OUTPUT BUS WIDTHS
- Publication number 20160306765
- Publication date Oct 20, 2016
- Avago Technologies General IP (Singapore) PTE. LTD.
- Darrin C. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modal PAM2/4 Pipelined Programmable Receiver Having Feed Forward Eq...
- Publication number 20150085914
- Publication date Mar 26, 2015
- Avago Technologies General IP (Singapore) PTE. LTD.
- Jade Michael Kizer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and Method For Adaptive N-Phase Clock Generation For An N-Ph...
- Publication number 20140362962
- Publication date Dec 11, 2014
- Peter J. Meier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Modal PAM2/PAM4 Divide By N (Div-N) Automatic Correlation Engine (A...
- Publication number 20140355658
- Publication date Dec 4, 2014
- Peter J. Meier
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FAST LOCK CLOCK-DATA RECOVERY FOR PHASE STEPS
- Publication number 20120250811
- Publication date Oct 4, 2012
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Brian J. Misek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Internal Loop-Back Architecture For Parallel Serializer/Deserialize...
- Publication number 20090213913
- Publication date Aug 27, 2009
- Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
- Michael Martin Farmer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System And Method For Equalizing Transition Density In An Integrate...
- Publication number 20090091369
- Publication date Apr 9, 2009
- Michael Martin Farmer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated Circuit Design Method for Efficiently Generating Mask Data
- Publication number 20080184188
- Publication date Jul 31, 2008
- Robert J. Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY-LOCKED LOOP AND A METHOD OF TESTING A DELAY-LOCKED LOOP
- Publication number 20070001661
- Publication date Jan 4, 2007
- Alvin Leng Sun LOKE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay-locked loop and a method of testing a delay-locked loop
- Publication number 20060139023
- Publication date Jun 29, 2006
- Alvin Leng Sun Loke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay-locked loop and a method of testing a delay-locked loop
- Publication number 20050280407
- Publication date Dec 22, 2005
- Alvin Leng Sun Loke
- H03 - BASIC ELECTRONIC CIRCUITRY

Peter J. Meier

Person

Patents Grantslast 30 patents

Low power parallelization to multiple output bus widths

System and method for high speed data parallelization for an N-phas...

Fast lock clock-data recovery for phase steps

Internal loop-back architecture for parallel serializer/deserialize...

System and method for equalizing transition density in an integrate...

Integrated circuit design method for efficiently generating mask data

Delay-locked loop and a method of testing a delay-locked loop

Delay-locked loop and a method of testing a delay-locked loop

Delay-locked loop and a method of testing a delay-locked loop

Integrated circuit with alternately selectable state evaluation pro...

Method and apparatus for low cost set mapping

Integrated circuit design system and method for generating a regula...

Symmetric edge true/complement buffer/inverter and method therefor

Patents Applicationslast 30 patents

LOW POWER PARALLELIZATION TO MULTIPLE OUTPUT BUS WIDTHS

Modal PAM2/4 Pipelined Programmable Receiver Having Feed Forward Eq...

System and Method For Adaptive N-Phase Clock Generation For An N-Ph...

Modal PAM2/PAM4 Divide By N (Div-N) Automatic Correlation Engine (A...

FAST LOCK CLOCK-DATA RECOVERY FOR PHASE STEPS

Internal Loop-Back Architecture For Parallel Serializer/Deserialize...

System And Method For Equalizing Transition Density In An Integrate...

Integrated Circuit Design Method for Efficiently Generating Mask Data

DELAY-LOCKED LOOP AND A METHOD OF TESTING A DELAY-LOCKED LOOP

Delay-locked loop and a method of testing a delay-locked loop

Delay-locked loop and a method of testing a delay-locked loop